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Searched refs:CPSR_N (Results 1 – 25 of 25) sorted by relevance

/dports/games/libretro-stella2014/stella2014-libretro-64f9364/stella/src/emucore/
H A DThumbulator.cxx381 if(x&0x80000000) cpsr|=CPSR_N; in do_nflag()
382 else cpsr&=~CPSR_N; in do_nflag()
731 if(cpsr&CPSR_N) in execute()
739 if(!(cpsr&CPSR_N)) in execute()
780 if( (cpsr&CPSR_N) && (cpsr&CPSR_V) ) ra++; in execute()
781 if((!(cpsr&CPSR_N))&&(!(cpsr&CPSR_V))) ra++; in execute()
791 if((!(cpsr&CPSR_N))&&(cpsr&CPSR_V)) ra++; in execute()
792 if((!(cpsr&CPSR_V))&&(cpsr&CPSR_N)) ra++; in execute()
802 if( (cpsr&CPSR_N) && (cpsr&CPSR_V) ) ra++; in execute()
814 if((!(cpsr&CPSR_N))&&(cpsr&CPSR_V)) ra++; in execute()
[all …]
H A DThumbulator.hxx56 #define CPSR_N (1<<31) macro
/dports/emulators/stella/stella-6.6/src/emucore/
H A DThumbulator.cxx776 if(x & 0x80000000) cpsr |= CPSR_N; else cpsr &= ~CPSR_N; in do_nflag()
1345 if(cpsr & CPSR_N) in execute()
1351 if(!(cpsr & CPSR_N)) in execute()
1381 if(((cpsr & CPSR_N) && (cpsr & CPSR_V)) || in execute()
1382 ((!(cpsr & CPSR_N)) && (!(cpsr & CPSR_V)))) in execute()
1388 if((!(cpsr & CPSR_N) && (cpsr & CPSR_V)) || in execute()
1389 (((cpsr & CPSR_N)) && !(cpsr & CPSR_V))) in execute()
1397 if(((cpsr & CPSR_N) && (cpsr & CPSR_V)) || in execute()
1398 ((!(cpsr & CPSR_N)) && (!(cpsr & CPSR_V)))) in execute()
1406 (!(cpsr & CPSR_N) && (cpsr & CPSR_V)) || in execute()
[all …]
H A DThumbulator.hxx43 #define CPSR_N (1u<<31) macro
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/
H A Dcpu.h250 #define CPSR_N (1 << 31) macro
251 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h456 #define CPSR_N (1U << 31) macro
457 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Dcpu.h456 #define CPSR_N (1U << 31) macro
457 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h1049 #define CPSR_N (1U << 31) macro
1050 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1075 #define XPSR_N CPSR_N
H A Dtranslate.c13159 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dcpu.h1163 #define CPSR_N (1U << 31) macro
1164 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1189 #define XPSR_N CPSR_N
H A Dcpu.c886 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dcpu.h1163 #define CPSR_N (1U << 31) macro
1164 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1189 #define XPSR_N CPSR_N
H A Dcpu.c886 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dcpu.h1243 #define CPSR_N (1U << 31) macro
1244 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1267 #define XPSR_N CPSR_N
H A Dcpu.c975 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dcpu.h1211 #define CPSR_N (1U << 31) macro
1212 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1235 #define XPSR_N CPSR_N
H A Dcpu.c996 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dcpu.h1211 #define CPSR_N (1U << 31) macro
1212 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1235 #define XPSR_N CPSR_N
H A Dcpu.c996 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dcpu.h1261 #define CPSR_N (1U << 31) macro
1262 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1285 #define XPSR_N CPSR_N
H A Dcpu.c995 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dcpu.h1273 #define CPSR_N (1U << 31) macro
1274 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1297 #define XPSR_N CPSR_N
H A Dcpu.c1017 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dcpu.h1273 #define CPSR_N (1U << 31) macro
1274 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1297 #define XPSR_N CPSR_N
H A Dcpu.c1017 psr & CPSR_N ? 'N' : '-', in arm_cpu_dump_state()