/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/ |
H A D | cpu.h | 236 #define CPSR_T (1 << 5) macro 254 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV) 258 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
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/dports/emulators/x49gp/x49gp/x49gp-code/qemu/patches/ |
H A D | qemu-0.9.0-x49gp-arm-dump-state.patch | 24 psr & CPSR_T ? 'T' : 'A',
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/dports/games/libretro-stella2014/stella2014-libretro-64f9364/stella/src/emucore/ |
H A D | Thumbulator.hxx | 53 #define CPSR_T (1<<5) macro
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/dports/devel/gdb/gdb-11.1/gdb/arch/ |
H A D | arm.h | 112 #define CPSR_T 0x20 macro
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/dports/emulators/qemu/qemu-6.2.0/linux-user/arm/ |
H A D | signal.c | 195 cpsr |= CPSR_T; in setup_return() 197 cpsr &= ~CPSR_T; in setup_return() 232 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/devel/avr-gdb/gdb-7.3.1/gdb/ |
H A D | arm-tdep.h | 110 #define CPSR_T 0x20 macro
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/dports/devel/gdb761/gdb-7.6.1/gdb/ |
H A D | arm-tdep.h | 113 #define CPSR_T 0x20 macro
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/dports/emulators/qemu42/qemu-4.2.1/linux-user/arm/ |
H A D | signal.c | 243 cpsr |= CPSR_T; in setup_return() 245 cpsr &= ~CPSR_T; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu60/qemu-6.0.0/linux-user/arm/ |
H A D | signal.c | 239 cpsr |= CPSR_T; in setup_return() 241 cpsr &= ~CPSR_T; in setup_return() 291 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-utils/qemu-4.2.1/linux-user/arm/ |
H A D | signal.c | 243 cpsr |= CPSR_T; in setup_return() 245 cpsr &= ~CPSR_T; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/linux-user/arm/ |
H A D | signal.c | 243 cpsr |= CPSR_T; in setup_return() 245 cpsr &= ~CPSR_T; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu5/qemu-5.2.0/linux-user/arm/ |
H A D | signal.c | 239 cpsr |= CPSR_T; in setup_return() 241 cpsr &= ~CPSR_T; in setup_return() 291 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/linux-user/arm/ |
H A D | signal.c | 243 cpsr |= CPSR_T; in setup_return() 245 cpsr &= ~CPSR_T; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/linux-user/arm/ |
H A D | signal.c | 240 cpsr |= CPSR_T; in setup_return() 242 cpsr &= ~CPSR_T; in setup_return() 292 cpsr_write(env, cpsr, CPSR_IT | CPSR_T | CPSR_E, CPSRWriteByInstr); in setup_return()
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/linux-user/arm/ |
H A D | signal.c | 243 cpsr |= CPSR_T; in setup_return() 245 cpsr &= ~CPSR_T; in setup_return() 290 cpsr_write(env, cpsr, CPSR_IT | CPSR_T, CPSRWriteByInstr); in setup_return()
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/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 436 #define CPSR_T (1U << 5) macro 461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 466 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/ |
H A D | cpu.h | 436 #define CPSR_T (1U << 5) macro 461 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 466 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
H A D | cpu.h | 1029 #define CPSR_T (1U << 5) macro 1054 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1059 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
H A D | cpu.h | 1143 #define CPSR_T (1U << 5) macro 1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1173 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
H A D | cpu.h | 1143 #define CPSR_T (1U << 5) macro 1168 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1173 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/devel/gdb/gdb-11.1/gdbserver/ |
H A D | linux-arm-low.cc | 902 *is_thumb = ((cpsr & CPSR_T) != 0); in arm_sigreturn_next_pc()
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
H A D | internals.h | 984 valid |= CPSR_T; in aarch32_cpsr_valid_mask()
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/dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
H A D | internals.h | 970 valid |= CPSR_T; in aarch32_cpsr_valid_mask()
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/dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
H A D | cpu.h | 1228 #define CPSR_T (1U << 5) macro 1248 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1253 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
H A D | cpu.h | 1196 #define CPSR_T (1U << 5) macro 1216 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ 1221 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
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