| /dports/devel/llvm80/llvm-8.0.1.src/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 868 unsigned CopyDstReg = 0;
872 CopyDstReg = MI.getOperand(0).getReg();
936 CopyDstReg = 0;
950 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg);
1001 CopyDstReg = 0; // cancel coalescing;
1003 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0;
1015 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) {
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 919 unsigned CopyDstReg = 0;
923 CopyDstReg = MI.getOperand(0).getReg();
987 CopyDstReg = 0;
1001 LiveRegMap::iterator LRI = reloadVirtReg(MI, I, Reg, CopyDstReg);
1053 CopyDstReg = 0; // cancel coalescing;
1055 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0;
1066 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) {
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 325 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
333 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
334 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
341 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 325 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
333 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
334 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
341 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
| H A D | AArch64RedundantCopyElimination.cpp | 324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg(); in optimizeBlock() local
332 OptBBClobberedRegs.available(CopyDstReg)) { in optimizeBlock()
333 KnownRegs.push_back(RegImm(CopyDstReg, KnownReg.Imm)); in optimizeBlock()
340 if (CopyDstReg == KnownReg.Reg && in optimizeBlock()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 965 Register CopyDstReg; in allocateInstruction() local
969 CopyDstReg = MI.getOperand(0).getReg(); in allocateInstruction()
1033 CopyDstReg = Register(); in allocateInstruction()
1059 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg); in allocateInstruction()
1138 CopyDstReg = Register(); // cancel coalescing; in allocateInstruction()
1140 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0; in allocateInstruction()
1152 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) { in allocateInstruction()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1018 Register CopyDstReg; in allocateInstruction() local
1022 CopyDstReg = MI.getOperand(0).getReg(); in allocateInstruction()
1086 CopyDstReg = Register(); in allocateInstruction()
1112 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg); in allocateInstruction()
1191 CopyDstReg = Register(); // cancel coalescing; in allocateInstruction()
1193 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0; in allocateInstruction()
1205 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) { in allocateInstruction()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1018 Register CopyDstReg; in allocateInstruction() local
1022 CopyDstReg = MI.getOperand(0).getReg(); in allocateInstruction()
1086 CopyDstReg = Register(); in allocateInstruction()
1112 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg); in allocateInstruction()
1191 CopyDstReg = Register(); // cancel coalescing; in allocateInstruction()
1193 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0; in allocateInstruction()
1205 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) { in allocateInstruction()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1018 Register CopyDstReg; in allocateInstruction() local
1022 CopyDstReg = MI.getOperand(0).getReg(); in allocateInstruction()
1086 CopyDstReg = Register(); in allocateInstruction()
1112 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg); in allocateInstruction()
1191 CopyDstReg = Register(); // cancel coalescing; in allocateInstruction()
1193 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0; in allocateInstruction()
1205 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) { in allocateInstruction()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1018 Register CopyDstReg; in allocateInstruction() local
1022 CopyDstReg = MI.getOperand(0).getReg(); in allocateInstruction()
1086 CopyDstReg = Register(); in allocateInstruction()
1112 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg); in allocateInstruction()
1191 CopyDstReg = Register(); // cancel coalescing; in allocateInstruction()
1193 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0; in allocateInstruction()
1205 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) { in allocateInstruction()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 1019 unsigned CopyDstReg = 0; in allocateInstruction() local
1023 CopyDstReg = MI.getOperand(0).getReg(); in allocateInstruction()
1087 CopyDstReg = 0; in allocateInstruction()
1112 LiveReg &LR = reloadVirtReg(MI, I, Reg, CopyDstReg); in allocateInstruction()
1191 CopyDstReg = 0; // cancel coalescing; in allocateInstruction()
1193 CopyDstReg = (CopyDstReg == Reg || CopyDstReg == PhysReg) ? PhysReg : 0; in allocateInstruction()
1205 if (CopyDstReg && CopyDstReg == CopySrcReg && CopyDstSub == CopySrcSub) { in allocateInstruction()
|