| /dports/sysutils/atf-sun50i_h6/arm-trusted-firmware-2.5/drivers/st/ddr/ |
| H A D | stm32mp1_ddr.c | 437 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in stm32mp1_wait_operating_mode()
443 DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
450 (operating_mode == DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
606 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
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| /dports/sysutils/atf-rk3399/arm-trusted-firmware-2.5/drivers/st/ddr/ |
| H A D | stm32mp1_ddr.c | 437 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in stm32mp1_wait_operating_mode()
443 DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
450 (operating_mode == DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
606 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
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| /dports/sysutils/atf-sun50i_a64/arm-trusted-firmware-2.5/drivers/st/ddr/ |
| H A D | stm32mp1_ddr.c | 437 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in stm32mp1_wait_operating_mode()
443 DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
450 (operating_mode == DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
606 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
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| /dports/sysutils/atf-rk3328/arm-trusted-firmware-2.5/drivers/st/ddr/ |
| H A D | stm32mp1_ddr.c | 437 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in stm32mp1_wait_operating_mode()
443 DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
450 (operating_mode == DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
606 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
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| /dports/sysutils/atf-fvp/arm-trusted-firmware-2.5/drivers/st/ddr/ |
| H A D | stm32mp1_ddr.c | 437 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in stm32mp1_wait_operating_mode()
443 DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
450 (operating_mode == DDRCTRL_STAT_OPERATING_MODE_SR) && in stm32mp1_wait_operating_mode()
606 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 313 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
320 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 313 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
320 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 313 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
320 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 313 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
320 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 313 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
320 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.c | 620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) { in wait_operating_mode()
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR | in wait_operating_mode()
|