1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #define LOG_CATEGORY UCLASS_RAM
7
8 #include <common.h>
9 #include <clk.h>
10 #include <log.h>
11 #include <ram.h>
12 #include <reset.h>
13 #include <timer.h>
14 #include <asm/io.h>
15 #include <asm/arch/ddr.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include <linux/iopoll.h>
19 #include "stm32mp1_ddr.h"
20 #include "stm32mp1_ddr_regs.h"
21
22 #define RCC_DDRITFCR 0xD8
23
24 #define RCC_DDRITFCR_DDRCAPBRST (BIT(14))
25 #define RCC_DDRITFCR_DDRCAXIRST (BIT(15))
26 #define RCC_DDRITFCR_DDRCORERST (BIT(16))
27 #define RCC_DDRITFCR_DPHYAPBRST (BIT(17))
28 #define RCC_DDRITFCR_DPHYRST (BIT(18))
29 #define RCC_DDRITFCR_DPHYCTLRST (BIT(19))
30
31 struct reg_desc {
32 const char *name;
33 u16 offset; /* offset for base address */
34 u8 par_offset; /* offset for parameter array */
35 };
36
37 #define INVALID_OFFSET 0xFF
38
39 #define DDRCTL_REG(x, y) \
40 {#x,\
41 offsetof(struct stm32mp1_ddrctl, x),\
42 offsetof(struct y, x)}
43
44 #define DDRPHY_REG(x, y) \
45 {#x,\
46 offsetof(struct stm32mp1_ddrphy, x),\
47 offsetof(struct y, x)}
48
49 #define DDR_REG_DYN(x) \
50 {#x,\
51 offsetof(struct stm32mp1_ddrctl, x),\
52 INVALID_OFFSET}
53
54 #define DDRPHY_REG_DYN(x) \
55 {#x,\
56 offsetof(struct stm32mp1_ddrphy, x),\
57 INVALID_OFFSET}
58
59 /***********************************************************
60 * PARAMETERS: value get from device tree :
61 * size / order need to be aligned with binding
62 * modification NOT ALLOWED !!!
63 ***********************************************************/
64 #define DDRCTL_REG_REG_SIZE 25 /* st,ctl-reg */
65 #define DDRCTL_REG_TIMING_SIZE 12 /* st,ctl-timing */
66 #define DDRCTL_REG_MAP_SIZE 9 /* st,ctl-map */
67 #define DDRCTL_REG_PERF_SIZE 17 /* st,ctl-perf */
68
69 #define DDRPHY_REG_REG_SIZE 11 /* st,phy-reg */
70 #define DDRPHY_REG_TIMING_SIZE 10 /* st,phy-timing */
71 #define DDRPHY_REG_CAL_SIZE 12 /* st,phy-cal */
72
73 #define DDRCTL_REG_REG(x) DDRCTL_REG(x, stm32mp1_ddrctrl_reg)
74 static const struct reg_desc ddr_reg[DDRCTL_REG_REG_SIZE] = {
75 DDRCTL_REG_REG(mstr),
76 DDRCTL_REG_REG(mrctrl0),
77 DDRCTL_REG_REG(mrctrl1),
78 DDRCTL_REG_REG(derateen),
79 DDRCTL_REG_REG(derateint),
80 DDRCTL_REG_REG(pwrctl),
81 DDRCTL_REG_REG(pwrtmg),
82 DDRCTL_REG_REG(hwlpctl),
83 DDRCTL_REG_REG(rfshctl0),
84 DDRCTL_REG_REG(rfshctl3),
85 DDRCTL_REG_REG(crcparctl0),
86 DDRCTL_REG_REG(zqctl0),
87 DDRCTL_REG_REG(dfitmg0),
88 DDRCTL_REG_REG(dfitmg1),
89 DDRCTL_REG_REG(dfilpcfg0),
90 DDRCTL_REG_REG(dfiupd0),
91 DDRCTL_REG_REG(dfiupd1),
92 DDRCTL_REG_REG(dfiupd2),
93 DDRCTL_REG_REG(dfiphymstr),
94 DDRCTL_REG_REG(odtmap),
95 DDRCTL_REG_REG(dbg0),
96 DDRCTL_REG_REG(dbg1),
97 DDRCTL_REG_REG(dbgcmd),
98 DDRCTL_REG_REG(poisoncfg),
99 DDRCTL_REG_REG(pccfg),
100 };
101
102 #define DDRCTL_REG_TIMING(x) DDRCTL_REG(x, stm32mp1_ddrctrl_timing)
103 static const struct reg_desc ddr_timing[DDRCTL_REG_TIMING_SIZE] = {
104 DDRCTL_REG_TIMING(rfshtmg),
105 DDRCTL_REG_TIMING(dramtmg0),
106 DDRCTL_REG_TIMING(dramtmg1),
107 DDRCTL_REG_TIMING(dramtmg2),
108 DDRCTL_REG_TIMING(dramtmg3),
109 DDRCTL_REG_TIMING(dramtmg4),
110 DDRCTL_REG_TIMING(dramtmg5),
111 DDRCTL_REG_TIMING(dramtmg6),
112 DDRCTL_REG_TIMING(dramtmg7),
113 DDRCTL_REG_TIMING(dramtmg8),
114 DDRCTL_REG_TIMING(dramtmg14),
115 DDRCTL_REG_TIMING(odtcfg),
116 };
117
118 #define DDRCTL_REG_MAP(x) DDRCTL_REG(x, stm32mp1_ddrctrl_map)
119 static const struct reg_desc ddr_map[DDRCTL_REG_MAP_SIZE] = {
120 DDRCTL_REG_MAP(addrmap1),
121 DDRCTL_REG_MAP(addrmap2),
122 DDRCTL_REG_MAP(addrmap3),
123 DDRCTL_REG_MAP(addrmap4),
124 DDRCTL_REG_MAP(addrmap5),
125 DDRCTL_REG_MAP(addrmap6),
126 DDRCTL_REG_MAP(addrmap9),
127 DDRCTL_REG_MAP(addrmap10),
128 DDRCTL_REG_MAP(addrmap11),
129 };
130
131 #define DDRCTL_REG_PERF(x) DDRCTL_REG(x, stm32mp1_ddrctrl_perf)
132 static const struct reg_desc ddr_perf[DDRCTL_REG_PERF_SIZE] = {
133 DDRCTL_REG_PERF(sched),
134 DDRCTL_REG_PERF(sched1),
135 DDRCTL_REG_PERF(perfhpr1),
136 DDRCTL_REG_PERF(perflpr1),
137 DDRCTL_REG_PERF(perfwr1),
138 DDRCTL_REG_PERF(pcfgr_0),
139 DDRCTL_REG_PERF(pcfgw_0),
140 DDRCTL_REG_PERF(pcfgqos0_0),
141 DDRCTL_REG_PERF(pcfgqos1_0),
142 DDRCTL_REG_PERF(pcfgwqos0_0),
143 DDRCTL_REG_PERF(pcfgwqos1_0),
144 DDRCTL_REG_PERF(pcfgr_1),
145 DDRCTL_REG_PERF(pcfgw_1),
146 DDRCTL_REG_PERF(pcfgqos0_1),
147 DDRCTL_REG_PERF(pcfgqos1_1),
148 DDRCTL_REG_PERF(pcfgwqos0_1),
149 DDRCTL_REG_PERF(pcfgwqos1_1),
150 };
151
152 #define DDRPHY_REG_REG(x) DDRPHY_REG(x, stm32mp1_ddrphy_reg)
153 static const struct reg_desc ddrphy_reg[DDRPHY_REG_REG_SIZE] = {
154 DDRPHY_REG_REG(pgcr),
155 DDRPHY_REG_REG(aciocr),
156 DDRPHY_REG_REG(dxccr),
157 DDRPHY_REG_REG(dsgcr),
158 DDRPHY_REG_REG(dcr),
159 DDRPHY_REG_REG(odtcr),
160 DDRPHY_REG_REG(zq0cr1),
161 DDRPHY_REG_REG(dx0gcr),
162 DDRPHY_REG_REG(dx1gcr),
163 DDRPHY_REG_REG(dx2gcr),
164 DDRPHY_REG_REG(dx3gcr),
165 };
166
167 #define DDRPHY_REG_TIMING(x) DDRPHY_REG(x, stm32mp1_ddrphy_timing)
168 static const struct reg_desc ddrphy_timing[DDRPHY_REG_TIMING_SIZE] = {
169 DDRPHY_REG_TIMING(ptr0),
170 DDRPHY_REG_TIMING(ptr1),
171 DDRPHY_REG_TIMING(ptr2),
172 DDRPHY_REG_TIMING(dtpr0),
173 DDRPHY_REG_TIMING(dtpr1),
174 DDRPHY_REG_TIMING(dtpr2),
175 DDRPHY_REG_TIMING(mr0),
176 DDRPHY_REG_TIMING(mr1),
177 DDRPHY_REG_TIMING(mr2),
178 DDRPHY_REG_TIMING(mr3),
179 };
180
181 #define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
182 static const struct reg_desc ddrphy_cal[DDRPHY_REG_CAL_SIZE] = {
183 DDRPHY_REG_CAL(dx0dllcr),
184 DDRPHY_REG_CAL(dx0dqtr),
185 DDRPHY_REG_CAL(dx0dqstr),
186 DDRPHY_REG_CAL(dx1dllcr),
187 DDRPHY_REG_CAL(dx1dqtr),
188 DDRPHY_REG_CAL(dx1dqstr),
189 DDRPHY_REG_CAL(dx2dllcr),
190 DDRPHY_REG_CAL(dx2dqtr),
191 DDRPHY_REG_CAL(dx2dqstr),
192 DDRPHY_REG_CAL(dx3dllcr),
193 DDRPHY_REG_CAL(dx3dqtr),
194 DDRPHY_REG_CAL(dx3dqstr),
195 };
196
197 /**************************************************************
198 * DYNAMIC REGISTERS: only used for debug purpose (read/modify)
199 **************************************************************/
200 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
201 static const struct reg_desc ddr_dyn[] = {
202 DDR_REG_DYN(stat),
203 DDR_REG_DYN(init0),
204 DDR_REG_DYN(dfimisc),
205 DDR_REG_DYN(dfistat),
206 DDR_REG_DYN(swctl),
207 DDR_REG_DYN(swstat),
208 DDR_REG_DYN(pctrl_0),
209 DDR_REG_DYN(pctrl_1),
210 };
211
212 #define DDR_REG_DYN_SIZE ARRAY_SIZE(ddr_dyn)
213
214 static const struct reg_desc ddrphy_dyn[] = {
215 DDRPHY_REG_DYN(pir),
216 DDRPHY_REG_DYN(pgsr),
217 DDRPHY_REG_DYN(zq0sr0),
218 DDRPHY_REG_DYN(zq0sr1),
219 DDRPHY_REG_DYN(dx0gsr0),
220 DDRPHY_REG_DYN(dx0gsr1),
221 DDRPHY_REG_DYN(dx1gsr0),
222 DDRPHY_REG_DYN(dx1gsr1),
223 DDRPHY_REG_DYN(dx2gsr0),
224 DDRPHY_REG_DYN(dx2gsr1),
225 DDRPHY_REG_DYN(dx3gsr0),
226 DDRPHY_REG_DYN(dx3gsr1),
227 };
228
229 #define DDRPHY_REG_DYN_SIZE ARRAY_SIZE(ddrphy_dyn)
230
231 #endif
232
233 /*****************************************************************
234 * REGISTERS ARRAY: used to parse device tree and interactive mode
235 *****************************************************************/
236 enum reg_type {
237 REG_REG,
238 REG_TIMING,
239 REG_PERF,
240 REG_MAP,
241 REGPHY_REG,
242 REGPHY_TIMING,
243 REGPHY_CAL,
244 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
245 /* dynamic registers => managed in driver or not changed,
246 * can be dumped in interactive mode
247 */
248 REG_DYN,
249 REGPHY_DYN,
250 #endif
251 REG_TYPE_NB
252 };
253
254 enum base_type {
255 DDR_BASE,
256 DDRPHY_BASE,
257 NONE_BASE
258 };
259
260 struct ddr_reg_info {
261 const char *name;
262 const struct reg_desc *desc;
263 u8 size;
264 enum base_type base;
265 };
266
267 #define DDRPHY_REG_CAL(x) DDRPHY_REG(x, stm32mp1_ddrphy_cal)
268
269 const struct ddr_reg_info ddr_registers[REG_TYPE_NB] = {
270 [REG_REG] = {
271 "static", ddr_reg, DDRCTL_REG_REG_SIZE, DDR_BASE},
272 [REG_TIMING] = {
273 "timing", ddr_timing, DDRCTL_REG_TIMING_SIZE, DDR_BASE},
274 [REG_PERF] = {
275 "perf", ddr_perf, DDRCTL_REG_PERF_SIZE, DDR_BASE},
276 [REG_MAP] = {
277 "map", ddr_map, DDRCTL_REG_MAP_SIZE, DDR_BASE},
278 [REGPHY_REG] = {
279 "static", ddrphy_reg, DDRPHY_REG_REG_SIZE, DDRPHY_BASE},
280 [REGPHY_TIMING] = {
281 "timing", ddrphy_timing, DDRPHY_REG_TIMING_SIZE, DDRPHY_BASE},
282 [REGPHY_CAL] = {
283 "cal", ddrphy_cal, DDRPHY_REG_CAL_SIZE, DDRPHY_BASE},
284 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
285 [REG_DYN] = {
286 "dyn", ddr_dyn, DDR_REG_DYN_SIZE, DDR_BASE},
287 [REGPHY_DYN] = {
288 "dyn", ddrphy_dyn, DDRPHY_REG_DYN_SIZE, DDRPHY_BASE},
289 #endif
290
291 };
292
293 const char *base_name[] = {
294 [DDR_BASE] = "ctl",
295 [DDRPHY_BASE] = "phy",
296 };
297
get_base_addr(const struct ddr_info * priv,enum base_type base)298 static u32 get_base_addr(const struct ddr_info *priv, enum base_type base)
299 {
300 if (base == DDRPHY_BASE)
301 return (u32)priv->phy;
302 else
303 return (u32)priv->ctl;
304 }
305
set_reg(const struct ddr_info * priv,enum reg_type type,const void * param)306 static void set_reg(const struct ddr_info *priv,
307 enum reg_type type,
308 const void *param)
309 {
310 unsigned int i;
311 unsigned int *ptr, value;
312 enum base_type base = ddr_registers[type].base;
313 u32 base_addr = get_base_addr(priv, base);
314 const struct reg_desc *desc = ddr_registers[type].desc;
315
316 log_debug("init %s\n", ddr_registers[type].name);
317 for (i = 0; i < ddr_registers[type].size; i++) {
318 ptr = (unsigned int *)(base_addr + desc[i].offset);
319 if (desc[i].par_offset == INVALID_OFFSET) {
320 log_err("invalid parameter offset for %s", desc[i].name);
321 } else {
322 value = *((u32 *)((u32)param +
323 desc[i].par_offset));
324 writel(value, ptr);
325 log_debug("[0x%x] %s= 0x%08x\n",
326 (u32)ptr, desc[i].name, value);
327 }
328 }
329 }
330
331 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
stm32mp1_dump_reg_desc(u32 base_addr,const struct reg_desc * desc)332 static void stm32mp1_dump_reg_desc(u32 base_addr, const struct reg_desc *desc)
333 {
334 unsigned int *ptr;
335
336 ptr = (unsigned int *)(base_addr + desc->offset);
337 printf("%s= 0x%08x\n", desc->name, readl(ptr));
338 }
339
stm32mp1_dump_param_desc(u32 par_addr,const struct reg_desc * desc)340 static void stm32mp1_dump_param_desc(u32 par_addr, const struct reg_desc *desc)
341 {
342 unsigned int *ptr;
343
344 ptr = (unsigned int *)(par_addr + desc->par_offset);
345 printf("%s= 0x%08x\n", desc->name, readl(ptr));
346 }
347
found_reg(const char * name,enum reg_type * type)348 static const struct reg_desc *found_reg(const char *name, enum reg_type *type)
349 {
350 unsigned int i, j;
351 const struct reg_desc *desc;
352
353 for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
354 desc = ddr_registers[i].desc;
355 for (j = 0; j < ddr_registers[i].size; j++) {
356 if (strcmp(name, desc[j].name) == 0) {
357 *type = i;
358 return &desc[j];
359 }
360 }
361 }
362 *type = REG_TYPE_NB;
363 return NULL;
364 }
365
stm32mp1_dump_reg(const struct ddr_info * priv,const char * name)366 int stm32mp1_dump_reg(const struct ddr_info *priv,
367 const char *name)
368 {
369 unsigned int i, j;
370 const struct reg_desc *desc;
371 u32 base_addr;
372 enum base_type p_base;
373 enum reg_type type;
374 const char *p_name;
375 enum base_type filter = NONE_BASE;
376 int result = -1;
377
378 if (name) {
379 if (strcmp(name, base_name[DDR_BASE]) == 0)
380 filter = DDR_BASE;
381 else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
382 filter = DDRPHY_BASE;
383 }
384
385 for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
386 p_base = ddr_registers[i].base;
387 p_name = ddr_registers[i].name;
388 if (!name || (filter == p_base || !strcmp(name, p_name))) {
389 result = 0;
390 desc = ddr_registers[i].desc;
391 base_addr = get_base_addr(priv, p_base);
392 printf("==%s.%s==\n", base_name[p_base], p_name);
393 for (j = 0; j < ddr_registers[i].size; j++)
394 stm32mp1_dump_reg_desc(base_addr, &desc[j]);
395 }
396 }
397 if (result) {
398 desc = found_reg(name, &type);
399 if (desc) {
400 p_base = ddr_registers[type].base;
401 base_addr = get_base_addr(priv, p_base);
402 stm32mp1_dump_reg_desc(base_addr, desc);
403 result = 0;
404 }
405 }
406 return result;
407 }
408
stm32mp1_edit_reg(const struct ddr_info * priv,char * name,char * string)409 void stm32mp1_edit_reg(const struct ddr_info *priv,
410 char *name, char *string)
411 {
412 unsigned long *ptr, value;
413 enum reg_type type;
414 enum base_type base;
415 const struct reg_desc *desc;
416 u32 base_addr;
417
418 desc = found_reg(name, &type);
419
420 if (!desc) {
421 printf("%s not found\n", name);
422 return;
423 }
424 if (strict_strtoul(string, 16, &value) < 0) {
425 printf("invalid value %s\n", string);
426 return;
427 }
428 base = ddr_registers[type].base;
429 base_addr = get_base_addr(priv, base);
430 ptr = (unsigned long *)(base_addr + desc->offset);
431 writel(value, ptr);
432 printf("%s= 0x%08x\n", desc->name, readl(ptr));
433 }
434
get_par_addr(const struct stm32mp1_ddr_config * config,enum reg_type type)435 static u32 get_par_addr(const struct stm32mp1_ddr_config *config,
436 enum reg_type type)
437 {
438 u32 par_addr = 0x0;
439
440 switch (type) {
441 case REG_REG:
442 par_addr = (u32)&config->c_reg;
443 break;
444 case REG_TIMING:
445 par_addr = (u32)&config->c_timing;
446 break;
447 case REG_PERF:
448 par_addr = (u32)&config->c_perf;
449 break;
450 case REG_MAP:
451 par_addr = (u32)&config->c_map;
452 break;
453 case REGPHY_REG:
454 par_addr = (u32)&config->p_reg;
455 break;
456 case REGPHY_TIMING:
457 par_addr = (u32)&config->p_timing;
458 break;
459 case REGPHY_CAL:
460 par_addr = (u32)&config->p_cal;
461 break;
462 case REG_DYN:
463 case REGPHY_DYN:
464 case REG_TYPE_NB:
465 par_addr = (u32)NULL;
466 break;
467 }
468
469 return par_addr;
470 }
471
stm32mp1_dump_param(const struct stm32mp1_ddr_config * config,const char * name)472 int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
473 const char *name)
474 {
475 unsigned int i, j;
476 const struct reg_desc *desc;
477 u32 par_addr;
478 enum base_type p_base;
479 enum reg_type type;
480 const char *p_name;
481 enum base_type filter = NONE_BASE;
482 int result = -EINVAL;
483
484 if (name) {
485 if (strcmp(name, base_name[DDR_BASE]) == 0)
486 filter = DDR_BASE;
487 else if (strcmp(name, base_name[DDRPHY_BASE]) == 0)
488 filter = DDRPHY_BASE;
489 }
490
491 for (i = 0; i < ARRAY_SIZE(ddr_registers); i++) {
492 par_addr = get_par_addr(config, i);
493 if (!par_addr)
494 continue;
495 p_base = ddr_registers[i].base;
496 p_name = ddr_registers[i].name;
497 if (!name || (filter == p_base || !strcmp(name, p_name))) {
498 result = 0;
499 desc = ddr_registers[i].desc;
500 printf("==%s.%s==\n", base_name[p_base], p_name);
501 for (j = 0; j < ddr_registers[i].size; j++)
502 stm32mp1_dump_param_desc(par_addr, &desc[j]);
503 }
504 }
505 if (result) {
506 desc = found_reg(name, &type);
507 if (desc) {
508 par_addr = get_par_addr(config, type);
509 if (par_addr) {
510 stm32mp1_dump_param_desc(par_addr, desc);
511 result = 0;
512 }
513 }
514 }
515 return result;
516 }
517
stm32mp1_edit_param(const struct stm32mp1_ddr_config * config,char * name,char * string)518 void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
519 char *name, char *string)
520 {
521 unsigned long *ptr, value;
522 enum reg_type type;
523 const struct reg_desc *desc;
524 u32 par_addr;
525
526 desc = found_reg(name, &type);
527 if (!desc) {
528 printf("%s not found\n", name);
529 return;
530 }
531 if (strict_strtoul(string, 16, &value) < 0) {
532 printf("invalid value %s\n", string);
533 return;
534 }
535 par_addr = get_par_addr(config, type);
536 if (!par_addr) {
537 printf("no parameter %s\n", name);
538 return;
539 }
540 ptr = (unsigned long *)(par_addr + desc->par_offset);
541 writel(value, ptr);
542 printf("%s= 0x%08x\n", desc->name, readl(ptr));
543 }
544 #endif
545
stm32mp1_ddr_interactive(void * priv,enum stm32mp1_ddr_interact_step step,const struct stm32mp1_ddr_config * config)546 __weak bool stm32mp1_ddr_interactive(void *priv,
547 enum stm32mp1_ddr_interact_step step,
548 const struct stm32mp1_ddr_config *config)
549 {
550 return false;
551 }
552
553 #define INTERACTIVE(step)\
554 stm32mp1_ddr_interactive(priv, step, config)
555
ddrphy_idone_wait(struct stm32mp1_ddrphy * phy)556 static void ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
557 {
558 u32 pgsr;
559 int ret;
560
561 ret = readl_poll_timeout(&phy->pgsr, pgsr,
562 pgsr & (DDRPHYC_PGSR_IDONE |
563 DDRPHYC_PGSR_DTERR |
564 DDRPHYC_PGSR_DTIERR |
565 DDRPHYC_PGSR_DFTERR |
566 DDRPHYC_PGSR_RVERR |
567 DDRPHYC_PGSR_RVEIRR),
568 1000000);
569 log_debug("\n[0x%08x] pgsr = 0x%08x ret=%d\n",
570 (u32)&phy->pgsr, pgsr, ret);
571 }
572
stm32mp1_ddrphy_init(struct stm32mp1_ddrphy * phy,u32 pir)573 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir)
574 {
575 pir |= DDRPHYC_PIR_INIT;
576 writel(pir, &phy->pir);
577 log_debug("[0x%08x] pir = 0x%08x -> 0x%08x\n",
578 (u32)&phy->pir, pir, readl(&phy->pir));
579
580 /* need to wait 10 configuration clock before start polling */
581 udelay(10);
582
583 /* Wait DRAM initialization and Gate Training Evaluation complete */
584 ddrphy_idone_wait(phy);
585 }
586
587 /* start quasi dynamic register update */
start_sw_done(struct stm32mp1_ddrctl * ctl)588 static void start_sw_done(struct stm32mp1_ddrctl *ctl)
589 {
590 clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
591 }
592
593 /* wait quasi dynamic register update */
wait_sw_done_ack(struct stm32mp1_ddrctl * ctl)594 static void wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
595 {
596 int ret;
597 u32 swstat;
598
599 setbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
600
601 ret = readl_poll_timeout(&ctl->swstat, swstat,
602 swstat & DDRCTRL_SWSTAT_SW_DONE_ACK,
603 1000000);
604 if (ret)
605 panic("Timeout initialising DRAM : DDR->swstat = %x\n",
606 swstat);
607
608 log_debug("[0x%08x] swstat = 0x%08x\n", (u32)&ctl->swstat, swstat);
609 }
610
611 /* wait quasi dynamic register update */
wait_operating_mode(struct ddr_info * priv,int mode)612 static void wait_operating_mode(struct ddr_info *priv, int mode)
613 {
614 u32 stat, val, mask, val2 = 0, mask2 = 0;
615 int ret;
616
617 mask = DDRCTRL_STAT_OPERATING_MODE_MASK;
618 val = mode;
619 /* self-refresh due to software => check also STAT.selfref_type */
620 if (mode == DDRCTRL_STAT_OPERATING_MODE_SR) {
621 mask |= DDRCTRL_STAT_SELFREF_TYPE_MASK;
622 val |= DDRCTRL_STAT_SELFREF_TYPE_SR;
623 } else if (mode == DDRCTRL_STAT_OPERATING_MODE_NORMAL) {
624 /* normal mode: handle also automatic self refresh */
625 mask2 = DDRCTRL_STAT_OPERATING_MODE_MASK |
626 DDRCTRL_STAT_SELFREF_TYPE_MASK;
627 val2 = DDRCTRL_STAT_OPERATING_MODE_SR |
628 DDRCTRL_STAT_SELFREF_TYPE_ASR;
629 }
630
631 ret = readl_poll_timeout(&priv->ctl->stat, stat,
632 ((stat & mask) == val) ||
633 (mask2 && ((stat & mask2) == val2)),
634 1000000);
635
636 if (ret)
637 panic("Timeout DRAM : DDR->stat = %x\n", stat);
638
639 log_debug("[0x%08x] stat = 0x%08x\n", (u32)&priv->ctl->stat, stat);
640 }
641
stm32mp1_refresh_disable(struct stm32mp1_ddrctl * ctl)642 void stm32mp1_refresh_disable(struct stm32mp1_ddrctl *ctl)
643 {
644 start_sw_done(ctl);
645 /* quasi-dynamic register update*/
646 setbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
647 clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN |
648 DDRCTRL_PWRCTL_SELFREF_EN);
649 clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
650 wait_sw_done_ack(ctl);
651 }
652
stm32mp1_refresh_restore(struct stm32mp1_ddrctl * ctl,u32 rfshctl3,u32 pwrctl)653 void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
654 u32 rfshctl3, u32 pwrctl)
655 {
656 start_sw_done(ctl);
657 if (!(rfshctl3 & DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH))
658 clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH);
659 if (pwrctl & DDRCTRL_PWRCTL_POWERDOWN_EN)
660 setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);
661 if ((pwrctl & DDRCTRL_PWRCTL_SELFREF_EN))
662 setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
663 setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
664 wait_sw_done_ack(ctl);
665 }
666
667 /* board-specific DDR power initializations. */
board_ddr_power_init(enum ddr_type ddr_type)668 __weak int board_ddr_power_init(enum ddr_type ddr_type)
669 {
670 return 0;
671 }
672
673 __maybe_unused
stm32mp1_ddr_init(struct ddr_info * priv,const struct stm32mp1_ddr_config * config)674 void stm32mp1_ddr_init(struct ddr_info *priv,
675 const struct stm32mp1_ddr_config *config)
676 {
677 u32 pir;
678 int ret = -EINVAL;
679 char bus_width;
680
681 switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) {
682 case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
683 bus_width = 8;
684 break;
685 case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
686 bus_width = 16;
687 break;
688 default:
689 bus_width = 32;
690 break;
691 }
692
693
694 if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
695 ret = board_ddr_power_init(STM32MP_DDR3);
696 else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) {
697 if (bus_width == 32)
698 ret = board_ddr_power_init(STM32MP_LPDDR2_32);
699 else
700 ret = board_ddr_power_init(STM32MP_LPDDR2_16);
701 } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) {
702 if (bus_width == 32)
703 ret = board_ddr_power_init(STM32MP_LPDDR3_32);
704 else
705 ret = board_ddr_power_init(STM32MP_LPDDR3_16);
706 }
707 if (ret)
708 panic("ddr power init failed\n");
709
710 start:
711 log_debug("name = %s\n", config->info.name);
712 log_debug("speed = %d kHz\n", config->info.speed);
713 log_debug("size = 0x%x\n", config->info.size);
714 /*
715 * 1. Program the DWC_ddr_umctl2 registers
716 * 1.1 RESETS: presetn, core_ddrc_rstn, aresetn
717 */
718 /* Assert All DDR part */
719 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
720 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
721 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
722 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
723 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
724 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
725
726 /* 1.2. start CLOCK */
727 if (stm32mp1_ddr_clk_enable(priv, config->info.speed))
728 panic("invalid DRAM clock : %d kHz\n",
729 config->info.speed);
730
731 /* 1.3. deassert reset */
732 /* de-assert PHY rstn and ctl_rstn via DPHYRST and DPHYCTLRST */
733 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST);
734 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST);
735 /* De-assert presetn once the clocks are active
736 * and stable via DDRCAPBRST bit
737 */
738 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
739
740 /* 1.4. wait 128 cycles to permit initialization of end logic */
741 udelay(2);
742 /* for PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
743
744 if (INTERACTIVE(STEP_DDR_RESET))
745 goto start;
746
747 /* 1.5. initialize registers ddr_umctl2 */
748 /* Stop uMCTL2 before PHY is ready */
749 clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
750 log_debug("[0x%08x] dfimisc = 0x%08x\n",
751 (u32)&priv->ctl->dfimisc, readl(&priv->ctl->dfimisc));
752
753 set_reg(priv, REG_REG, &config->c_reg);
754 set_reg(priv, REG_TIMING, &config->c_timing);
755 set_reg(priv, REG_MAP, &config->c_map);
756
757 /* skip CTRL init, SDRAM init is done by PHY PUBL */
758 clrsetbits_le32(&priv->ctl->init0,
759 DDRCTRL_INIT0_SKIP_DRAM_INIT_MASK,
760 DDRCTRL_INIT0_SKIP_DRAM_INIT_NORMAL);
761
762 set_reg(priv, REG_PERF, &config->c_perf);
763
764 if (INTERACTIVE(STEP_CTL_INIT))
765 goto start;
766
767 /* 2. deassert reset signal core_ddrc_rstn, aresetn and presetn */
768 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST);
769 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST);
770 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST);
771
772 /* 3. start PHY init by accessing relevant PUBL registers
773 * (DXGCR, DCR, PTR*, MR*, DTPR*)
774 */
775 set_reg(priv, REGPHY_REG, &config->p_reg);
776 set_reg(priv, REGPHY_TIMING, &config->p_timing);
777 if (config->p_cal_present)
778 set_reg(priv, REGPHY_CAL, &config->p_cal);
779
780 if (INTERACTIVE(STEP_PHY_INIT))
781 goto start;
782
783 /* 4. Monitor PHY init status by polling PUBL register PGSR.IDONE
784 * Perform DDR PHY DRAM initialization and Gate Training Evaluation
785 */
786 ddrphy_idone_wait(priv->phy);
787
788 /* 5. Indicate to PUBL that controller performs SDRAM initialization
789 * by setting PIR.INIT and PIR CTLDINIT and pool PGSR.IDONE
790 * DRAM init is done by PHY, init0.skip_dram.init = 1
791 */
792 pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL |
793 DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_DRAMINIT | DDRPHYC_PIR_ICPC;
794
795 if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
796 pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */
797
798 stm32mp1_ddrphy_init(priv->phy, pir);
799
800 /* 6. SET DFIMISC.dfi_init_complete_en to 1 */
801 /* Enable quasi-dynamic register programming*/
802 start_sw_done(priv->ctl);
803 setbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
804 wait_sw_done_ack(priv->ctl);
805
806 /* 7. Wait for DWC_ddr_umctl2 to move to normal operation mode
807 * by monitoring STAT.operating_mode signal
808 */
809 /* wait uMCTL2 ready */
810
811 wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL);
812
813 if (config->p_cal_present) {
814 log_debug("DDR DQS training skipped.\n");
815 } else {
816 log_debug("DDR DQS training : ");
817 /* 8. Disable Auto refresh and power down by setting
818 * - RFSHCTL3.dis_au_refresh = 1
819 * - PWRCTL.powerdown_en = 0
820 * - DFIMISC.dfiinit_complete_en = 0
821 */
822 stm32mp1_refresh_disable(priv->ctl);
823
824 /* 9. Program PUBL PGCR to enable refresh during training and rank to train
825 * not done => keep the programed value in PGCR
826 */
827
828 /* 10. configure PUBL PIR register to specify which training step to run */
829 /* warning : RVTRN is not supported by this PUBL */
830 stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
831
832 /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
833 ddrphy_idone_wait(priv->phy);
834
835 /* 12. set back registers in step 8 to the orginal values if desidered */
836 stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,
837 config->c_reg.pwrctl);
838 } /* if (config->p_cal_present) */
839
840 /* enable uMCTL2 AXI port 0 and 1 */
841 setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);
842 setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);
843
844 if (INTERACTIVE(STEP_DDR_READY))
845 goto start;
846 }
847