| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 17 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
143 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 15 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
302 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 15 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
302 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 15 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
302 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 15 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
302 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-mvebu/ |
| H A D | cpu.c | 19 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3)) macro
333 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i)); in update_sdram_window_sizes()
|