Searched refs:DSP48A1 (Results 1 – 15 of 15) sorted by relevance
/dports/cad/yosys/yosys-yosys-0.12/tests/arch/xilinx/ |
H A D | dsp_cascade.ys | 41 select -assert-count 3 t:DSP48A1 43 select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D 46 select -assert-count 2 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i 81 select -assert-count 2 t:DSP48A1 85 select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D 88 select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i
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H A D | mul.ys | 20 select -assert-count 1 t:DSP48A1 21 select -assert-none t:DSP48A1 %% t:* %D
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H A D | mul_unsigned.ys | 23 select -assert-count 1 t:DSP48A1 25 select -assert-none t:DSP48A1 t:FDRE t:BUFG %% t:* %D
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/dports/cad/yosys/yosys-yosys-0.12/passes/pmgen/ |
H A D | xilinx_dsp_cascade.pmg | 67 …select (first->type.in(\DSP48A, \DSP48A1) && port(first, \OPMODE, Const(0, 8)).extract(2,2) == Con… 100 if (dsp->type.in(\DSP48A, \DSP48A1)) { 135 if (dsp->type.in(\DSP48A, \DSP48A1)) { 137 // "The DSP48A1 component uses this input when cascading 138 // BCOUT from an adjacent DSP48A1 slice. The tools then 157 // of the DSP48A1 slice. If the B port is connected to the 158 // BCOUT of another DSP48A1 slice, then the tools automatically 190 …select (nextP->type.in(\DSP48A, \DSP48A1) && port(nextP, \OPMODE, Const(0, 8)).extract(2,2) == Con… 286 if ((next->type.in(\DSP48A, \DSP48A1) && param(prev, \B0REG) == 0 && param(prev, \B1REG) == 0) || 301 if (next->type.in(\DSP48A, \DSP48A1)) [all …]
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H A D | xilinx_dsp48a.pmg | 3 // DSP48A/DSP48A1 (Spartan 3A DSP, Spartan 6). 5 // ( 1) Starting from a DSP48A/DSP48A1 cell 51 // (1) Starting from a DSP48A/DSP48A1 cell 53 select dsp->type.in(\DSP48A, \DSP48A1)
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H A D | xilinx_dsp_CREG.pmg | 41 select dsp->type.in(\DSP48A, \DSP48A1, \DSP48E1)
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/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/ |
H A D | xc6s_dsp_map.v | 9 DSP48A1 #(
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H A D | cells_sim.v | 2613 DSP48A1 #( 2665 module DSP48A1 ( module
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/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/tests/ |
H A D | test_dsp48a1_model.sh | 8 cp $ISE_DIR/ISE_DS/ISE/verilog/src/unisims/DSP48A1.v test_dsp48a1_model_ref.v
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H A D | test_dsp48a1_model.v | 184 DSP48A1 #(
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/dsp/ |
H A D | add_then_mac.v | 121 DSP48A1 #(
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen_dsp/ |
H A D | hbdec1.v | 23338 DSP48A1 #( 23464 DSP48A1 #( 23590 DSP48A1 #( 23716 DSP48A1 #( 23842 DSP48A1 #( 23968 DSP48A1 #( 24094 DSP48A1 #( 24220 DSP48A1 #( 24346 DSP48A1 #( 24472 DSP48A1 #( [all …]
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H A D | hbdec2.v | 14829 DSP48A1 #( 14955 DSP48A1 #( 15081 DSP48A1 #( 15207 DSP48A1 #( 15333 DSP48A1 #( 15459 DSP48A1 #( 15585 DSP48A1 #( 15711 DSP48A1 #( 15837 DSP48A1 #( 15963 DSP48A1 #( [all …]
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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen_dsp/ |
H A D | hbdec1.v | 23338 DSP48A1 #( 23464 DSP48A1 #( 23590 DSP48A1 #( 23716 DSP48A1 #( 23842 DSP48A1 #( 23968 DSP48A1 #( 24094 DSP48A1 #( 24220 DSP48A1 #( 24346 DSP48A1 #( 24472 DSP48A1 #( [all …]
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H A D | hbdec2.v | 14829 DSP48A1 #( 14955 DSP48A1 #( 15081 DSP48A1 #( 15207 DSP48A1 #( 15333 DSP48A1 #( 15459 DSP48A1 #( 15585 DSP48A1 #( 15711 DSP48A1 #( 15837 DSP48A1 #( 15963 DSP48A1 #( [all …]
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