1read_verilog mul_unsigned.v 2hierarchy -top mul_unsigned 3proc 4 5equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check 6design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 7cd mul_unsigned # Constrain all select calls below inside the top module 8select -assert-count 1 t:BUFG 9select -assert-count 1 t:DSP48E1 10select -assert-count 30 t:FDRE 11select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D 12 13design -reset 14 15read_verilog mul_unsigned.v 16hierarchy -top mul_unsigned 17proc 18 19equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check 20design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) 21cd mul_unsigned # Constrain all select calls below inside the top module 22select -assert-count 1 t:BUFG 23select -assert-count 1 t:DSP48A1 24select -assert-count 30 t:FDRE 25select -assert-none t:DSP48A1 t:FDRE t:BUFG %% t:* %D 26