| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/cpu/ |
| H A D | initcode.c | 151 # error invalid EBIU_RSTCTL value: must not set reserved bits
218 #ifndef EBIU_RSTCTL
322 #ifdef EBIU_RSTCTL in maybe_self_refresh()
354 #ifdef EBIU_RSTCTL in program_clocks()
513 #ifndef EBIU_RSTCTL in program_memory_controller()
529 #ifdef EBIU_RSTCTL in program_memory_controller()
540 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/cpu/ |
| H A D | initcode.c | 151 # error invalid EBIU_RSTCTL value: must not set reserved bits
218 #ifndef EBIU_RSTCTL
322 #ifdef EBIU_RSTCTL in maybe_self_refresh()
354 #ifdef EBIU_RSTCTL in program_clocks()
513 #ifndef EBIU_RSTCTL in program_memory_controller()
529 #ifdef EBIU_RSTCTL in program_memory_controller()
540 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/cpu/ |
| H A D | initcode.c | 151 # error invalid EBIU_RSTCTL value: must not set reserved bits
218 #ifndef EBIU_RSTCTL
322 #ifdef EBIU_RSTCTL in maybe_self_refresh()
354 #ifdef EBIU_RSTCTL in program_clocks()
513 #ifndef EBIU_RSTCTL in program_memory_controller()
529 #ifdef EBIU_RSTCTL in program_memory_controller()
540 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/cpu/ |
| H A D | initcode.c | 151 # error invalid EBIU_RSTCTL value: must not set reserved bits
218 #ifndef EBIU_RSTCTL
322 #ifdef EBIU_RSTCTL in maybe_self_refresh()
354 #ifdef EBIU_RSTCTL in program_clocks()
513 #ifndef EBIU_RSTCTL in program_memory_controller()
529 #ifdef EBIU_RSTCTL in program_memory_controller()
540 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/cpu/ |
| H A D | initcode.c | 151 # error invalid EBIU_RSTCTL value: must not set reserved bits
218 #ifndef EBIU_RSTCTL
322 #ifdef EBIU_RSTCTL in maybe_self_refresh()
354 #ifdef EBIU_RSTCTL in program_clocks()
513 #ifndef EBIU_RSTCTL in program_memory_controller()
529 #ifdef EBIU_RSTCTL in program_memory_controller()
540 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/cpu/ |
| H A D | initcode.c | 151 # error invalid EBIU_RSTCTL value: must not set reserved bits
218 #ifndef EBIU_RSTCTL
322 #ifdef EBIU_RSTCTL in maybe_self_refresh()
354 #ifdef EBIU_RSTCTL in program_clocks()
513 #ifndef EBIU_RSTCTL in program_memory_controller()
529 #ifdef EBIU_RSTCTL in program_memory_controller()
540 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/cpu/ |
| H A D | initcode.c | 151 # error invalid EBIU_RSTCTL value: must not set reserved bits
218 #ifndef EBIU_RSTCTL
322 #ifdef EBIU_RSTCTL in maybe_self_refresh()
354 #ifdef EBIU_RSTCTL in program_clocks()
513 #ifndef EBIU_RSTCTL in program_memory_controller()
529 #ifdef EBIU_RSTCTL in program_memory_controller()
540 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/cpu/ |
| H A D | initcode.c | 378 #ifndef EBIU_RSTCTL
524 #if defined(EBIU_RSTCTL) in maybe_self_refresh()
588 #if defined(EBIU_RSTCTL) in program_clocks()
859 #if defined(EBIU_RSTCTL) in program_memory_controller()
870 #ifdef EBIU_RSTCTL in program_memory_controller()
|
| H A D | initcode.h | 24 # error invalid EBIU_RSTCTL value: must not set reserved bits
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/common/ |
| H A D | cmd_reginfo.c | 207 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/common/ |
| H A D | cmd_reginfo.c | 207 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/common/ |
| H A D | cmd_reginfo.c | 207 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/common/ |
| H A D | cmd_reginfo.c | 207 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/common/ |
| H A D | cmd_reginfo.c | 207 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/common/ |
| H A D | cmd_reginfo.c | 207 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/common/ |
| H A D | cmd_reginfo.c | 207 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/common/ |
| H A D | cmd_reginfo.c | 197 # ifdef EBIU_RSTCTL in do_reginfo()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/blackfin/include/asm/mach-bf548/ |
| H A D | ADSP-EDN-BF547-extended_def.h | 479 #define EBIU_RSTCTL 0xFFC00A3C /* DDR Reset Control Register */ macro
|