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Searched refs:EltReg (Results 1 – 15 of 15) sorted by relevance

/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp96 Register EltReg, unsigned LaneIdx,
3494 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
3505 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
3509 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3517 .addUse(EltReg); in emitLaneInsert()
3534 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
3535 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
3550 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
3567 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp151 Register EltReg, unsigned LaneIdx,
4848 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4859 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4871 .addUse(EltReg); in emitLaneInsert()
4953 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4954 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4969 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4985 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB); in selectInsertElt()
5094 Register EltReg = I.getOperand(1).getReg(); in tryOptBuildVecToSubregToReg() local
5095 LLT EltTy = MRI.getType(EltReg); in tryOptBuildVecToSubregToReg()
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp111 Register EltReg, unsigned LaneIdx,
3865 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
3876 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
3880 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3888 .addUse(EltReg); in emitLaneInsert()
3905 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
3906 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
3921 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
3938 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp111 Register EltReg, unsigned LaneIdx,
3865 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
3876 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
3880 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3888 .addUse(EltReg); in emitLaneInsert()
3905 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
3906 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
3921 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
3938 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp111 Register EltReg, unsigned LaneIdx,
3865 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
3876 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
3880 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
3888 .addUse(EltReg); in emitLaneInsert()
3905 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
3906 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
3921 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
3938 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp129 Register EltReg, unsigned LaneIdx,
4410 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4421 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4425 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4433 .addUse(EltReg); in emitLaneInsert()
4450 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4451 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4466 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4483 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp126 Register EltReg, unsigned LaneIdx,
4386 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4397 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4401 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4409 .addUse(EltReg); in emitLaneInsert()
4426 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4427 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4442 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4459 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp126 Register EltReg, unsigned LaneIdx,
4387 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4398 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4402 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4410 .addUse(EltReg); in emitLaneInsert()
4427 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4428 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4443 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4460 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp150 Register EltReg, unsigned LaneIdx,
4773 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4784 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4796 .addUse(EltReg); in emitLaneInsert()
4813 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4814 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4829 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4845 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB); in selectInsertElt()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp150 Register EltReg, unsigned LaneIdx,
4773 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4784 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4796 .addUse(EltReg); in emitLaneInsert()
4813 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4814 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4829 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4845 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB); in selectInsertElt()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp139 Register EltReg, unsigned LaneIdx,
4659 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4670 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4674 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4682 .addUse(EltReg); in emitLaneInsert()
4699 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4700 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4715 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4732 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp150 Register EltReg, unsigned LaneIdx,
4773 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4784 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4796 .addUse(EltReg); in emitLaneInsert()
4813 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4814 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4829 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4845 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB); in selectInsertElt()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp150 Register EltReg, unsigned LaneIdx,
4773 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4784 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4796 .addUse(EltReg); in emitLaneInsert()
4813 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4814 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4829 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4845 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB); in selectInsertElt()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp139 Register EltReg, unsigned LaneIdx,
4659 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4670 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4674 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4682 .addUse(EltReg); in emitLaneInsert()
4699 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4700 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4715 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4732 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIRBuilder); in selectInsertElt()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp150 Register EltReg, unsigned LaneIdx,
4773 Optional<Register> DstReg, Register SrcReg, Register EltReg, in emitLaneInsert() argument
4784 unsigned EltSize = MRI.getType(EltReg).getSizeInBits(); in emitLaneInsert()
4788 auto InsSub = emitScalarToVector(EltSize, DstRC, EltReg, MIRBuilder); in emitLaneInsert()
4796 .addUse(EltReg); in emitLaneInsert()
4813 Register EltReg = I.getOperand(2).getReg(); in selectInsertElt() local
4814 const LLT EltTy = MRI.getType(EltReg); in selectInsertElt()
4829 const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI); in selectInsertElt()
4845 emitLaneInsert(None, SrcReg, EltReg, LaneIdx, EltRB, MIB); in selectInsertElt()