/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2461 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2466 ExtraCC = AArch64CC::EQ; in selectBranch() 2470 ExtraCC = AArch64CC::MI; in selectBranch() 2477 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2479 .addImm(ExtraCC) in selectBranch() 2742 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2792 ExtraCC = AArch64CC::EQ; in selectSelect() 2796 ExtraCC = AArch64CC::MI; in selectSelect() 2826 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2828 Src2IsKill, ExtraCC); in selectSelect()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2461 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2466 ExtraCC = AArch64CC::EQ; in selectBranch() 2470 ExtraCC = AArch64CC::MI; in selectBranch() 2477 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2479 .addImm(ExtraCC) in selectBranch() 2742 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2792 ExtraCC = AArch64CC::EQ; in selectSelect() 2796 ExtraCC = AArch64CC::MI; in selectSelect() 2826 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2828 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 2129 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 2130 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 2133 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 2139 ExtraCC, DL, DAG); in emitConjunctionRec() 2141 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2408 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2413 ExtraCC = AArch64CC::EQ; in selectBranch() 2417 ExtraCC = AArch64CC::MI; in selectBranch() 2424 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2426 .addImm(ExtraCC) in selectBranch() 2685 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2732 ExtraCC = AArch64CC::EQ; in selectSelect() 2736 ExtraCC = AArch64CC::MI; in selectSelect() 2762 if (ExtraCC != AArch64CC::AL) in selectSelect() 2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2408 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2413 ExtraCC = AArch64CC::EQ; in selectBranch() 2417 ExtraCC = AArch64CC::MI; in selectBranch() 2424 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2426 .addImm(ExtraCC) in selectBranch() 2685 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2732 ExtraCC = AArch64CC::EQ; in selectSelect() 2736 ExtraCC = AArch64CC::MI; in selectSelect() 2762 if (ExtraCC != AArch64CC::AL) in selectSelect() 2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2461 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2466 ExtraCC = AArch64CC::EQ; in selectBranch() 2470 ExtraCC = AArch64CC::MI; in selectBranch() 2477 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2479 .addImm(ExtraCC) in selectBranch() 2742 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2792 ExtraCC = AArch64CC::EQ; in selectSelect() 2796 ExtraCC = AArch64CC::MI; in selectSelect() 2826 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2828 Src2IsKill, ExtraCC); in selectSelect()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2461 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2466 ExtraCC = AArch64CC::EQ; in selectBranch() 2470 ExtraCC = AArch64CC::MI; in selectBranch() 2477 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2479 .addImm(ExtraCC) in selectBranch() 2742 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2792 ExtraCC = AArch64CC::EQ; in selectSelect() 2796 ExtraCC = AArch64CC::MI; in selectSelect() 2826 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2828 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 2132 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 2133 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 2136 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 2142 ExtraCC, DL, DAG); in emitConjunctionRec() 2144 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2463 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2468 ExtraCC = AArch64CC::EQ; in selectBranch() 2472 ExtraCC = AArch64CC::MI; in selectBranch() 2479 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2481 .addImm(ExtraCC) in selectBranch() 2744 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2794 ExtraCC = AArch64CC::EQ; in selectSelect() 2798 ExtraCC = AArch64CC::MI; in selectSelect() 2828 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2830 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 1932 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 1933 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 1936 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 1942 ExtraCC, DL, DAG); in emitConjunctionRec() 1944 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2408 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2413 ExtraCC = AArch64CC::EQ; in selectBranch() 2417 ExtraCC = AArch64CC::MI; in selectBranch() 2424 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2426 .addImm(ExtraCC) in selectBranch() 2685 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2732 ExtraCC = AArch64CC::EQ; in selectSelect() 2736 ExtraCC = AArch64CC::MI; in selectSelect() 2762 if (ExtraCC != AArch64CC::AL) in selectSelect() 2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2463 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2468 ExtraCC = AArch64CC::EQ; in selectBranch() 2472 ExtraCC = AArch64CC::MI; in selectBranch() 2479 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2481 .addImm(ExtraCC) in selectBranch() 2744 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2794 ExtraCC = AArch64CC::EQ; in selectSelect() 2798 ExtraCC = AArch64CC::MI; in selectSelect() 2828 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2830 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 1932 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 1933 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 1936 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 1942 ExtraCC, DL, DAG); in emitConjunctionRec() 1944 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2408 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2413 ExtraCC = AArch64CC::EQ; in selectBranch() 2417 ExtraCC = AArch64CC::MI; in selectBranch() 2424 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2426 .addImm(ExtraCC) in selectBranch() 2685 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2732 ExtraCC = AArch64CC::EQ; in selectSelect() 2736 ExtraCC = AArch64CC::MI; in selectSelect() 2762 if (ExtraCC != AArch64CC::AL) in selectSelect() 2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2408 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2413 ExtraCC = AArch64CC::EQ; in selectBranch() 2417 ExtraCC = AArch64CC::MI; in selectBranch() 2424 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2426 .addImm(ExtraCC) in selectBranch() 2685 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2732 ExtraCC = AArch64CC::EQ; in selectSelect() 2736 ExtraCC = AArch64CC::MI; in selectSelect() 2762 if (ExtraCC != AArch64CC::AL) in selectSelect() 2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2463 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2468 ExtraCC = AArch64CC::EQ; in selectBranch() 2472 ExtraCC = AArch64CC::MI; in selectBranch() 2479 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2481 .addImm(ExtraCC) in selectBranch() 2744 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2794 ExtraCC = AArch64CC::EQ; in selectSelect() 2798 ExtraCC = AArch64CC::MI; in selectSelect() 2828 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2830 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 1932 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 1933 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 1936 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 1942 ExtraCC, DL, DAG); in emitConjunctionRec() 1944 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2461 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2466 ExtraCC = AArch64CC::EQ; in selectBranch() 2470 ExtraCC = AArch64CC::MI; in selectBranch() 2477 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2479 .addImm(ExtraCC) in selectBranch() 2742 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2792 ExtraCC = AArch64CC::EQ; in selectSelect() 2796 ExtraCC = AArch64CC::MI; in selectSelect() 2826 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2828 Src2IsKill, ExtraCC); in selectSelect()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2426 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2431 ExtraCC = AArch64CC::EQ; in selectBranch() 2435 ExtraCC = AArch64CC::MI; in selectBranch() 2442 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2444 .addImm(ExtraCC) in selectBranch() 2707 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2757 ExtraCC = AArch64CC::EQ; in selectSelect() 2761 ExtraCC = AArch64CC::MI; in selectSelect() 2791 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2793 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 1756 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 1757 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 1760 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 1766 ExtraCC, DL, DAG); in emitConjunctionRec() 1768 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2430 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2435 ExtraCC = AArch64CC::EQ; in selectBranch() 2439 ExtraCC = AArch64CC::MI; in selectBranch() 2446 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2448 .addImm(ExtraCC) in selectBranch() 2711 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2761 ExtraCC = AArch64CC::EQ; in selectSelect() 2765 ExtraCC = AArch64CC::MI; in selectSelect() 2795 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2797 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 1725 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 1726 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 1729 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 1735 ExtraCC, DL, DAG); in emitConjunctionRec() 1737 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2421 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2426 ExtraCC = AArch64CC::EQ; in selectBranch() 2430 ExtraCC = AArch64CC::MI; in selectBranch() 2437 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2439 .addImm(ExtraCC) in selectBranch() 2702 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2752 ExtraCC = AArch64CC::EQ; in selectSelect() 2756 ExtraCC = AArch64CC::MI; in selectSelect() 2786 if (ExtraCC != AArch64CC::AL) { in selectSelect() 2788 Src2IsKill, ExtraCC); in selectSelect()
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H A D | AArch64ISelLowering.cpp | 1693 AArch64CC::CondCode ExtraCC; in emitConjunctionRec() local 1694 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC); in emitConjunctionRec() 1697 if (ExtraCC != AArch64CC::AL) { in emitConjunctionRec() 1703 ExtraCC, DL, DAG); in emitConjunctionRec() 1705 Predicate = ExtraCC; in emitConjunctionRec()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 2408 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectBranch() local 2413 ExtraCC = AArch64CC::EQ; in selectBranch() 2417 ExtraCC = AArch64CC::MI; in selectBranch() 2424 if (ExtraCC != AArch64CC::AL) { in selectBranch() 2426 .addImm(ExtraCC) in selectBranch() 2685 AArch64CC::CondCode ExtraCC = AArch64CC::AL; in selectSelect() local 2732 ExtraCC = AArch64CC::EQ; in selectSelect() 2736 ExtraCC = AArch64CC::MI; in selectSelect() 2762 if (ExtraCC != AArch64CC::AL) in selectSelect() 2763 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, ExtraCC); in selectSelect()
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