/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 898 Register ForwardedReg = F.PReg; in lowerTailCall() local 901 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 904 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 909 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 910 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
H A D | AArch64CallLowering.cpp | 877 Register ForwardedReg = F.PReg; in lowerTailCall() local 880 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 883 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 888 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 889 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 863 Register ForwardedReg = F.PReg; in lowerTailCall() local 866 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 869 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 874 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 875 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
H A D | AArch64CallLowering.cpp | 877 Register ForwardedReg = F.PReg; in lowerTailCall() local 880 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 883 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 888 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 889 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CallLowering.cpp | 877 Register ForwardedReg = F.PReg; in lowerTailCall() local 880 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 883 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 888 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 889 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 863 Register ForwardedReg = F.PReg; in lowerTailCall() local 866 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 869 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 874 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 875 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 901 Register ForwardedReg = F.PReg; in lowerTailCall() local 904 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 907 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 912 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 913 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 903 Register ForwardedReg = F.PReg; in lowerTailCall() local 906 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 909 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 914 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 915 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 990 Register ForwardedReg = F.PReg; in lowerTailCall() local 993 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 996 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 1001 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 1002 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 990 Register ForwardedReg = F.PReg; in lowerTailCall() local 993 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 996 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 1001 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 1002 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 990 Register ForwardedReg = F.PReg; in lowerTailCall() local 993 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 996 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 1001 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 1002 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 1028 Register ForwardedReg = F.PReg; in lowerTailCall() local 1031 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 1034 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 1039 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 1040 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 990 Register ForwardedReg = F.PReg; in lowerTailCall() local 993 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 996 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 1001 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 1002 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 990 Register ForwardedReg = F.PReg; in lowerTailCall() local 993 if (any_of(MIB->uses(), [&ForwardedReg, &TRI](const MachineOperand &Use) { in lowerTailCall() 996 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall() 1001 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall() 1002 MIB.addReg(ForwardedReg, RegState::Implicit); in lowerTailCall()
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