ICC_AP1R_EL1 (reference) in projects: dports

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Searched refs:ICC_AP1R_EL1 (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/qemu42/qemu-4.2.1/hw/intc/
H A D	arm_gicv3_kvm.c	64 #define ICC_AP1R_EL1(n) \ macro 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put() 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put() 498 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put() 501 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put() 645 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get() 647 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get() 650 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get() 653 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()
/dports/emulators/qemu/qemu-6.2.0/hw/intc/
H A D	arm_gicv3_kvm.c	62 #define ICC_AP1R_EL1(n) \ macro 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put() 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put() 499 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put() 503 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put() 649 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get() 651 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get() 655 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get() 659 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()
/dports/emulators/qemu60/qemu-6.0.0/hw/intc/
H A D	arm_gicv3_kvm.c	63 #define ICC_AP1R_EL1(n) \ macro 494 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put() 496 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put() 500 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put() 504 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put() 650 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get() 652 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get() 656 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get() 660 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/hw/intc/
H A D	arm_gicv3_kvm.c	63 #define ICC_AP1R_EL1(n) \ macro 495 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put() 497 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put() 500 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put() 503 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put() 647 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get() 649 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get() 652 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get() 655 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()
/dports/emulators/qemu5/qemu-5.2.0/hw/intc/
H A D	arm_gicv3_kvm.c	63 #define ICC_AP1R_EL1(n) \ macro 492 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put() 494 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put() 497 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put() 500 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put() 644 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get() 646 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get() 649 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get() 652 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()
/dports/emulators/qemu-utils/qemu-4.2.1/hw/intc/
H A D	arm_gicv3_kvm.c	64 #define ICC_AP1R_EL1(n) \ macro 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put() 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put() 498 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put() 501 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put() 645 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get() 647 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get() 650 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get() 653 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/hw/intc/
H A D	arm_gicv3_kvm.c	64 #define ICC_AP1R_EL1(n) \ 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); 498 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); 501 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); 645 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); 647 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); 650 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); 653 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false);
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/hw/intc/
H A D	arm_gicv3_kvm.c	64 #define ICC_AP1R_EL1(n) \ macro 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); in kvm_arm_gicv3_put() 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); in kvm_arm_gicv3_put() 498 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); in kvm_arm_gicv3_put() 501 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); in kvm_arm_gicv3_put() 645 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); in kvm_arm_gicv3_get() 647 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); in kvm_arm_gicv3_get() 650 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); in kvm_arm_gicv3_get() 653 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false); in kvm_arm_gicv3_get()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/hw/intc/
H A D	arm_gicv3_kvm.c	62 #define ICC_AP1R_EL1(n) \ 493 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, true); 495 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, true); 499 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, true); 503 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, true); 649 kvm_gicc_access(s, ICC_AP1R_EL1(3), ncpu, &reg64, false); 651 kvm_gicc_access(s, ICC_AP1R_EL1(2), ncpu, &reg64, false); 655 kvm_gicc_access(s, ICC_AP1R_EL1(1), ncpu, &reg64, false); 659 kvm_gicc_access(s, ICC_AP1R_EL1(0), ncpu, &reg64, false);