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Searched refs:I_MASK (Results 1 – 25 of 192) sorted by relevance

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/dports/databases/libiodbc/iODBC-3.52.15/iodbc/trace/
H A DInfo.c101 #define I_MASK(T) case T: \ macro
1441 I_MASK (SQL_ALTER_TABLE); in _trace_getinfo()
1461 I_MASK (SQL_LOCK_TYPES); in _trace_getinfo()
1519 I_MASK (SQL_SUBQUERIES); in _trace_getinfo()
1525 I_MASK (SQL_UNION); in _trace_getinfo()
1580 I_MASK (SQL_CREATE_VIEW); in _trace_getinfo()
1586 I_MASK (SQL_DDL_INDEX); in _trace_getinfo()
1600 I_MASK (SQL_DROP_DOMAIN); in _trace_getinfo()
1602 I_MASK (SQL_DROP_SCHEMA); in _trace_getinfo()
1604 I_MASK (SQL_DROP_TABLE); in _trace_getinfo()
[all …]
/dports/emulators/mess/mame-mame0226/src/devices/cpu/arm7/
H A Darm7core.hxx120 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
136 set_cpsr(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */ in arm7_check_irq_state()
145 if (m_pendingIrq && (cpsr & I_MASK) == 0) in arm7_check_irq_state()
152 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
175 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
199 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
224 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
/dports/emulators/mame/mame-mame0226/src/devices/cpu/arm7/
H A Darm7core.hxx120 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
136 set_cpsr(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */ in arm7_check_irq_state()
145 if (m_pendingIrq && (cpsr & I_MASK) == 0) in arm7_check_irq_state()
152 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
175 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
199 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
224 set_cpsr(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/ic/
H A Disacsx.c506 ISAC_WRITE(I_MASK, 0xff); in isic_isacsx_l1_cmd()
511 ISAC_WRITE(I_MASK, isacsx_imask); in isic_isacsx_l1_cmd()
565 ISAC_WRITE(I_MASK, isacsx_imask); in isic_isacsx_init()
614 ISAC_WRITE(I_MASK, isacsx_imask); in isic_isacsx_init()
630 ISAC_WRITE(I_MASK, isacsx_imask); in isic_isacsx_disable_intr()
671 ISAC_WRITE(I_MASK, 0xff); in isic_isacsx_recover()
674 ISAC_WRITE(I_MASK, isacsx_imask); in isic_isacsx_recover()
H A Disac.c498 ISAC_WRITE(I_MASK, 0xff); in isic_isac_l1_cmd()
502 ISAC_WRITE(I_MASK, ISAC_IMASK); in isic_isac_l1_cmd()
557 ISAC_WRITE(I_MASK, ISAC_IMASK); in isic_isac_init()
661 ISAC_WRITE(I_MASK, ISAC_IMASK); in isic_isac_init()
723 ISAC_WRITE(I_MASK, 0xff); in isic_recover()
725 ISAC_WRITE(I_MASK, ISAC_IMASK); in isic_recover()
H A Disic.c146 ISAC_WRITE(I_MASK, 0xff); in isicintr()
157 ISAC_WRITE(I_MASK, ISAC_IMASK); in isicintr()
/dports/devel/gdb/gdb-11.1/gdb/nat/
H A Dmips-linux-watch.h85 #define I_MASK (1 << I_BIT) macro
87 #define IRW_MASK (I_MASK | R_MASK | W_MASK)
/dports/devel/dev86/dev86-0.16.20/ld/
H A Ddumps.c58 if (((flags = symptr->flags) & (C_MASK | I_MASK)) == I_MASK) in dumpsyms()
H A Dwritebin.c215 if (!(symptr->flags & (I_MASK | SA_MASK)))
235 if (!reloc_output || !(symptr->flags & I_MASK))
357 if (!reloc_output || !(symptr->flags & I_MASK))
364 if (!reloc_output || !(symptr->flags & I_MASK))
489 else if (flags & (E_MASK | I_MASK))
493 if (!(flags & I_MASK) || (
775 if (!reloc_output || !(symptr->flags & I_MASK))
797 if (symptr->flags & I_MASK)
874 if (symptr->flags != (I_MASK | curseg) || symptr->value != 0)
H A Dobj.h44 #define I_MASK 0x0040 /* imported */ macro
H A Dwritex86.c184 if (!(symptr->flags & (I_MASK | SA_MASK)))
398 else if (flags & (E_MASK | I_MASK))
402 if (!(flags & I_MASK) ||
606 if (symptr->flags != (I_MASK | curseg) || symptr->value != 0)
/dports/emulators/mess/mame-mame0226/src/devices/cpu/e132xs/
H A D32xsdefs.h164 #define I_MASK 0x00000080 macro
186 #define GET_I ((SR & I_MASK)>>7) // bit 7 //INTERRUPT-MODE
204 #define SET_I(val) (SR = (SR & ~I_MASK) | ((val) << 7))
/dports/emulators/mame/mame-mame0226/src/devices/cpu/e132xs/
H A D32xsdefs.h164 #define I_MASK 0x00000080 macro
186 #define GET_I ((SR & I_MASK)>>7) // bit 7 //INTERRUPT-MODE
204 #define SET_I(val) (SR = (SR & ~I_MASK) | ((val) << 7))
/dports/games/libretro-fbneo/FBNeo-bbe3c05/src/cpu/arm7/
H A Darm7core.c562 SET_CPSR(GET_CPSR | I_MASK | F_MASK | 0x10); in arm7_core_reset()
592 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
605 SET_CPSR(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */ in arm7_check_irq_state()
613 if (ARM7.pendingIrq && (cpsr & I_MASK) == 0) { in arm7_check_irq_state()
617 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
629 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
642 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
663 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/cpu/arm7/
H A Darm7core.c562 SET_CPSR(GET_CPSR | I_MASK | F_MASK | 0x10); in arm7_core_reset()
592 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
605 SET_CPSR(GET_CPSR | I_MASK | F_MASK); /* Mask both IRQ & FIQ */ in arm7_check_irq_state()
613 if (ARM7.pendingIrq && (cpsr & I_MASK) == 0) { in arm7_check_irq_state()
617 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
629 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
642 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
663 SET_CPSR(GET_CPSR | I_MASK); /* Mask IRQ */ in arm7_check_irq_state()
/dports/emulators/mess/mame-mame0226/src/devices/cpu/arm/
H A Darm.cpp100 #define I_MASK ((uint32_t)(1<<I_BIT)) /* Interrupt request disable */ macro
107 #define I_IS_SET(pc) ((pc) & I_MASK)
333 R15 = eARM_MODE_SVC|I_MASK|F_MASK; in device_reset()
433 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in execute_run()
465 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state()
470 if (m_pendingIrq && (pc&I_MASK)==0) in arm_check_irq_state()
474 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state()
562 (m_sArmRegister[15] & I_MASK) ? 'I' : '-', in state_string_export()
/dports/emulators/mame/mame-mame0226/src/devices/cpu/arm/
H A Darm.cpp100 #define I_MASK ((uint32_t)(1<<I_BIT)) /* Interrupt request disable */ macro
107 #define I_IS_SET(pc) ((pc) & I_MASK)
333 R15 = eARM_MODE_SVC|I_MASK|F_MASK; in device_reset()
433 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in execute_run()
465 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state()
470 if (m_pendingIrq && (pc&I_MASK)==0) in arm_check_irq_state()
474 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state()
562 (m_sArmRegister[15] & I_MASK) ? 'I' : '-', in state_string_export()
/dports/games/libretro-fbneo/FBNeo-bbe3c05/src/cpu/arm/
H A Darm.cpp118 #define I_MASK ((UINT32)(1<<I_BIT)) /* Interrupt request disable */ macro
125 #define I_IS_SET(pc) ((pc) & I_MASK)
329 R15 = eARM_MODE_SVC|I_MASK|F_MASK; in ArmReset()
430 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in ArmRun()
471 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state()
476 if (arm.pendingIrq && (pc&I_MASK)==0) { in arm_check_irq_state()
479 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state()
/dports/games/libretro-fbalpha/fbalpha-84eb9d9/src/cpu/arm/
H A Darm.cpp118 #define I_MASK ((UINT32)(1<<I_BIT)) /* Interrupt request disable */ macro
125 #define I_IS_SET(pc) ((pc) & I_MASK)
329 R15 = eARM_MODE_SVC|I_MASK|F_MASK; in ArmReset()
427 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in ArmRun()
463 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state()
468 if (arm.pendingIrq && (pc&I_MASK)==0) { in arm_check_irq_state()
471 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state()
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pcmcia/
H A Disic_pcmcia_elsa_isdnmc.c109 ISAC_WRITE(I_MASK, 0xff); in elsa_isdnmc_clrirq()
112 ISAC_WRITE(I_MASK, ISAC_IMASK); in elsa_isdnmc_clrirq()
/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/cpu/arm/
H A Darm.c99 #define I_MASK ((data32_t)(1<<I_BIT)) /* Interrupt request disable */ macro
106 #define I_IS_SET(pc) ((pc) & I_MASK)
297 R15 = eARM_MODE_SVC|I_MASK|F_MASK; in arm_reset()
542 R15 = (pc&PSR_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set PC=0x1c */ in arm_check_irq_state()
546 if (arm.pendingIrq && (pc&I_MASK)==0) { in arm_check_irq_state()
549 R15 = (pc&PSR_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=0x18 */ in arm_check_irq_state()
661 (pRegs->sArmRegister[15] & I_MASK) ? 'I' : '-', in arm_info()
/dports/games/libretro-mame2003_plus/mame2003-plus-libretro-17e9889/src/cpu/arm/
H A Darm.c100 #define I_MASK ((data32_t)(1<<I_BIT)) /* Interrupt request disable */ macro
107 #define I_IS_SET(pc) ((pc) & I_MASK)
302 R15 = eARM_MODE_SVC|I_MASK|F_MASK; in arm_reset()
409 R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK); in arm_execute()
554 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x1c|eARM_MODE_FIQ|I_MASK|F_MASK; /* Mask both IRQ & FIRQ, set P… in arm_check_irq_state()
559 if (arm.pendingIrq && (pc&I_MASK)==0) { in arm_check_irq_state()
562 …R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x18|eARM_MODE_IRQ|I_MASK|(pc&F_MASK); /* Mask only IRQ, set PC=… in arm_check_irq_state()
675 (pRegs->sArmRegister[15] & I_MASK) ? 'I' : '-', in arm_info()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/include/bedbug/
H A Dtables.h95 { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
97 { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
99 { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
101 { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/include/bedbug/
H A Dtables.h95 { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
97 { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
99 { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
101 { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/include/bedbug/
H A Dtables.h95 { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0},
97 { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0},
99 { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0},
101 { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0},

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