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Searched refs:L2_CACHE_ENABLE (Results 1 – 25 of 119) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/riscv/cpu/fu540/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/riscv/cpu/fu740/
H A Dcache.c16 #define L2_CACHE_ENABLE 0x008 macro
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE); in cache_enable_ways()

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