1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020-2021 SiFive, Inc
4 *
5 * Authors:
6 * Pragnesh Patel <pragnesh.patel@sifive.com>
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <linux/bitops.h>
12 #include <asm/global_data.h>
13
14 /* Register offsets */
15 #define L2_CACHE_CONFIG 0x000
16 #define L2_CACHE_ENABLE 0x008
17
18 #define MASK_NUM_WAYS GENMASK(15, 8)
19 #define NUM_WAYS_SHIFT 8
20
21 DECLARE_GLOBAL_DATA_PTR;
22
cache_enable_ways(void)23 int cache_enable_ways(void)
24 {
25 const void *blob = gd->fdt_blob;
26 int node;
27 fdt_addr_t base;
28 u32 config;
29 u32 ways;
30
31 volatile u32 *enable;
32
33 node = fdt_node_offset_by_compatible(blob, -1,
34 "sifive,fu740-c000-ccache");
35
36 if (node < 0)
37 return node;
38
39 base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
40 NULL, false);
41 if (base == FDT_ADDR_T_NONE)
42 return FDT_ADDR_T_NONE;
43
44 config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
45 ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
46
47 enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
48
49 /* memory barrier */
50 mb();
51 (*enable) = ways - 1;
52 /* memory barrier */
53 mb();
54 return 0;
55 }
56