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Searched refs:MDCR_SPME (Results 1 – 17 of 17) sorted by relevance

/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Dcpu.h1014 #define MDCR_SPME (1U << 17) macro
1026 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Dcpu.h1126 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1140 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1320 (env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Dcpu.h1126 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1140 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1320 (env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Dcpu.h1211 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1225 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1456 !(env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Dcpu.h1179 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1193 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1507 (env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Dcpu.h1179 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1193 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1507 (env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Dcpu.h1227 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1241 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1467 !(env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Dcpu.h1239 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1253 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1423 !(env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Dcpu.h1239 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ macro
1253 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
H A Dhelper.c1199 !(env->cp15.mdcr_el3 & MDCR_SPME); in pmu_counter_enabled()