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Searched refs:MDIO_PORT0 (Results 1 – 25 of 59) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/pci/
H A Dpcie_brcmstb.c112 #define MDIO_PORT0 0x0 macro
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp); in brcm_pcie_set_ssc()
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp); in brcm_pcie_set_ssc()
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp); in brcm_pcie_set_ssc()

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