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Searched refs:MO_FPU (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/ext/armips/Archs/MIPS/
H A DMipsOpcodes.cpp104 { "lwc1", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
105 { "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
106 { "l.s", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
107 { "l.s", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
132 { "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
133 { "s.s", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
134 { "s.s", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
381 { "mfc1", "t,S", MIPS_COP1(0x00), MA_MIPS1, MO_FPU },
383 { "cfc1", "t,f", MIPS_COP1(0x02), MA_MIPS1, MO_FPU },
384 { "mtc1", "t,S", MIPS_COP1(0x04), MA_MIPS1, MO_FPU },
[all …]
H A DMipsOpcodes.h36 #define MO_FPU 0x00020000 // only available with an fpu macro
H A DMipsParser.cpp1482 if ((MipsOpcodes[z].flags & MO_FPU) && !(arch.flags & MO_FPU)) in parseOpcode()
/dports/emulators/ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/
H A DMipsOpcodes.cpp104 { "lwc1", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
105 { "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
106 { "l.s", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
107 { "l.s", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
132 { "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
133 { "s.s", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
134 { "s.s", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
381 { "mfc1", "t,S", MIPS_COP1(0x00), MA_MIPS1, MO_FPU },
383 { "cfc1", "t,f", MIPS_COP1(0x02), MA_MIPS1, MO_FPU },
384 { "mtc1", "t,S", MIPS_COP1(0x04), MA_MIPS1, MO_FPU },
[all …]
H A DMipsOpcodes.h36 #define MO_FPU 0x00020000 // only available with an fpu macro
H A DMipsParser.cpp1482 if ((MipsOpcodes[z].flags & MO_FPU) && !(arch.flags & MO_FPU)) in parseOpcode()
/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/
H A DMipsOpcodes.cpp104 { "lwc1", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
105 { "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
106 { "l.s", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
107 { "l.s", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
132 { "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
133 { "s.s", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
134 { "s.s", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
381 { "mfc1", "t,S", MIPS_COP1(0x00), MA_MIPS1, MO_FPU },
383 { "cfc1", "t,f", MIPS_COP1(0x02), MA_MIPS1, MO_FPU },
384 { "mtc1", "t,S", MIPS_COP1(0x04), MA_MIPS1, MO_FPU },
[all …]
H A DMipsOpcodes.h36 #define MO_FPU 0x00020000 // only available with an fpu macro
H A DMipsParser.cpp1482 if ((MipsOpcodes[z].flags & MO_FPU) && !(arch.flags & MO_FPU)) in parseOpcode()