1 #include "stdafx.h" 2 #include "MipsOpcodes.h" 3 4 const tMipsOpcode MipsOpcodes[] = { 5 // 31---------26---------------------------------------------------0 6 // | opcode | | 7 // ------6---------------------------------------------------------- 8 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 9 // 000 | *1 | *2 | J | JAL | BEQ | BNE | BLEZ | BGTZ | 00..07 10 // 001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI | 08..0F 11 // 010 | *3 | *4 | *5 | --- | BEQL | BNEL | BLEZL | BGTZL | 10..17 12 // 011 | DADDI | DADDIU| LDL | LDR | --- | --- | LQ | SQ | 18..1F 13 // 100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU | 20..27 14 // 101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE | 28..2F 15 // 110 | LL | LWC1 | LV.S | --- | LLD | ULV.Q | LV.Q | LD | 30..37 16 // 111 | SC | SWC1 | SV.S | --- | SCD | USV.Q | SV.Q | SD | 38..3F 17 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 18 // *1 = SPECIAL *2 = REGIMM *3 = COP0 *4 = COP1 *5 = COP2 19 { "j", "i26", MIPS_OP(0x02), MA_MIPS1, MO_IPCA|MO_DELAY|MO_NODELAYSLOT }, 20 { "jal", "i26", MIPS_OP(0x03), MA_MIPS1, MO_IPCA|MO_DELAY|MO_NODELAYSLOT }, 21 { "beq", "s,t,i16", MIPS_OP(0x04), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 22 { "beqz", "s,i16", MIPS_OP(0x04), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 23 { "b", "i16", MIPS_OP(0x04), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 24 { "bne", "s,t,i16", MIPS_OP(0x05), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 25 { "bnez", "s,i16", MIPS_OP(0x05), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 26 { "blez", "s,i16", MIPS_OP(0x06), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 27 { "bgtz", "s,i16", MIPS_OP(0x07), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 28 { "addi", "t,s,i16", MIPS_OP(0x08), MA_MIPS1, MO_IGNORERTD }, 29 { "addi", "s,i16", MIPS_OP(0x08), MA_MIPS1, MO_RST }, 30 { "subi", "t,s,i16", MIPS_OP(0x08), MA_MIPS1, MO_IGNORERTD|MO_NEGIMM }, 31 { "subi", "s,i16", MIPS_OP(0x08), MA_MIPS1, MO_RST|MO_NEGIMM }, 32 { "addiu", "t,s,i16", MIPS_OP(0x09), MA_MIPS1, MO_IGNORERTD }, 33 { "addiu", "s,i16", MIPS_OP(0x09), MA_MIPS1, MO_RST }, 34 { "subiu", "t,s,i16", MIPS_OP(0x09), MA_MIPS1, MO_IGNORERTD|MO_NEGIMM }, 35 { "subiu", "s,i16", MIPS_OP(0x09), MA_MIPS1, MO_RST|MO_NEGIMM }, 36 { "slti", "t,s,i16", MIPS_OP(0x0A), MA_MIPS1, MO_IGNORERTD }, 37 { "slti", "s,i16", MIPS_OP(0x0A), MA_MIPS1, MO_RST }, 38 { "sltiu", "t,s,i16", MIPS_OP(0x0B), MA_MIPS1, MO_IGNORERTD }, 39 { "sltiu", "s,i16", MIPS_OP(0x0B), MA_MIPS1, MO_RST }, 40 { "andi", "t,s,i16", MIPS_OP(0x0C), MA_MIPS1, MO_IGNORERTD }, 41 { "andi", "s,i16", MIPS_OP(0x0C), MA_MIPS1, MO_RST }, 42 { "ori", "t,s,i16", MIPS_OP(0x0D), MA_MIPS1, MO_IGNORERTD }, 43 { "ori", "s,i16", MIPS_OP(0x0D), MA_MIPS1, MO_RST }, 44 { "xori", "t,s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_IGNORERTD }, 45 { "xori", "s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_RST }, 46 { "lui", "t,i16", MIPS_OP(0x0F), MA_MIPS1, MO_IGNORERTD }, 47 { "cop2", "i25", MIPS_OP(0x12)|(1<<25), MA_PSX, 0 }, 48 { "beql", "s,t,i16", MIPS_OP(0x14), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 49 { "beqzl", "s,i16", MIPS_OP(0x14), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 50 { "bnel", "s,t,i16", MIPS_OP(0x15), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 51 { "bnezl", "s,i16", MIPS_OP(0x15), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 52 { "blezl", "s,i16", MIPS_OP(0x16), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 53 { "bgtzl", "s,i16", MIPS_OP(0x17), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 54 { "daddi", "t,s,i16", MIPS_OP(0x18), MA_MIPS3, MO_64BIT }, 55 { "daddi", "s,i16", MIPS_OP(0x18), MA_MIPS3, MO_64BIT|MO_RST }, 56 { "dsubi", "t,s,i16", MIPS_OP(0x18), MA_MIPS3, MO_64BIT|MO_NEGIMM }, 57 { "dsubi", "s,i16", MIPS_OP(0x18), MA_MIPS3, MO_64BIT|MO_RST|MO_NEGIMM }, 58 { "daddiu", "t,s,i16", MIPS_OP(0x19), MA_MIPS3, MO_64BIT }, 59 { "daddiu", "s,i16", MIPS_OP(0x19), MA_MIPS3, MO_64BIT|MO_RST }, 60 { "dsubiu", "t,s,i16", MIPS_OP(0x19), MA_MIPS3, MO_64BIT|MO_NEGIMM }, 61 { "dsubiu", "s,i16", MIPS_OP(0x19), MA_MIPS3, MO_64BIT|MO_RST|MO_NEGIMM }, 62 { "ldl", "t,i16(s)", MIPS_OP(0x1A), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD }, 63 { "ldl", "t,(s)", MIPS_OP(0x1A), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD }, 64 { "ldr", "t,i16(s)", MIPS_OP(0x1B), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD }, 65 { "ldr", "t,(s)", MIPS_OP(0x1B), MA_MIPS3, MO_64BIT|MO_DELAYRT|MO_IGNORERTD }, 66 { "lq", "t,i16(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 67 { "lq", "t,(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 68 { "sq", "t,i16(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 69 { "sq", "t,(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 70 { "lb", "t,i16(s)", MIPS_OP(0x20), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 71 { "lb", "t,(s)", MIPS_OP(0x20), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 72 { "lh", "t,i16(s)", MIPS_OP(0x21), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 73 { "lh", "t,(s)", MIPS_OP(0x21), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 74 { "lwl", "t,i16(s)", MIPS_OP(0x22), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 75 { "lwl", "t,(s)", MIPS_OP(0x22), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 76 { "lw", "t,i16(s)", MIPS_OP(0x23), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 77 { "lw", "t,(s)", MIPS_OP(0x23), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 78 { "lbu", "t,i16(s)", MIPS_OP(0x24), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 79 { "lbu", "t,(s)", MIPS_OP(0x24), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 80 { "lhu", "t,i16(s)", MIPS_OP(0x25), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 81 { "lhu", "t,(s)", MIPS_OP(0x25), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 82 { "lwr", "t,i16(s)", MIPS_OP(0x26), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 83 { "lwr", "t,(s)", MIPS_OP(0x26), MA_MIPS1, MO_DELAYRT|MO_IGNORERTD }, 84 { "lwu", "t,i16(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 85 { "lwu", "t,(s)", MIPS_OP(0x27), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 86 { "sb", "t,i16(s)", MIPS_OP(0x28), MA_MIPS1, 0 }, 87 { "sb", "t,(s)", MIPS_OP(0x28), MA_MIPS1, 0 }, 88 { "sh", "t,i16(s)", MIPS_OP(0x29), MA_MIPS1, 0 }, 89 { "sh", "t,(s)", MIPS_OP(0x29), MA_MIPS1, 0 }, 90 { "swl", "t,i16(s)", MIPS_OP(0x2A), MA_MIPS1, 0 }, 91 { "swl", "t,(s)", MIPS_OP(0x2A), MA_MIPS1, 0 }, 92 { "sw", "t,i16(s)", MIPS_OP(0x2B), MA_MIPS1, 0 }, 93 { "sw", "t,(s)", MIPS_OP(0x2B), MA_MIPS1, 0 }, 94 { "sdl", "t,i16(s)", MIPS_OP(0x2C), MA_MIPS3, MO_64BIT }, 95 { "sdl", "t,(s)", MIPS_OP(0x2C), MA_MIPS3, MO_64BIT }, 96 { "sdr", "t,i16(s)", MIPS_OP(0x2D), MA_MIPS3, MO_64BIT|MO_IGNORERTD }, 97 { "sdr", "t,(s)", MIPS_OP(0x2D), MA_MIPS3, MO_64BIT|MO_IGNORERTD }, 98 { "swr", "t,i16(s)", MIPS_OP(0x2E), MA_MIPS1, 0 }, 99 { "swr", "t,(s)", MIPS_OP(0x2E), MA_MIPS1, 0 }, 100 { "cache", "jc,i16(s)", MIPS_OP(0x2F), MA_MIPS2, 0 }, 101 { "cache", "jc,(s)", MIPS_OP(0x2F), MA_MIPS2, 0 }, 102 { "ll", "t,i16(s)", MIPS_OP(0x30), MA_MIPS2, MO_DELAYRT|MO_IGNORERTD }, 103 { "ll", "t,(s)", MIPS_OP(0x30), MA_MIPS2, MO_DELAYRT|MO_IGNORERTD }, 104 { "lwc1", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU }, 105 { "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU }, 106 { "l.s", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU }, 107 { "l.s", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU }, 108 { "lwc2", "gt,i16(s)", MIPS_OP(0x32), MA_PSX, 0 }, 109 { "lwc2", "gt,(s)", MIPS_OP(0x32), MA_PSX, 0 }, 110 { "lv.s", "vt,i16(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED }, 111 { "lv.s", "vt,(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED }, 112 { "lld", "t,i16(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 113 { "lld", "t,(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 114 { "ldc1", "T,i16(s)", MIPS_OP(0x35), MA_MIPS2, MO_DFPU }, 115 { "ldc1", "T,(s)", MIPS_OP(0x35), MA_MIPS2, MO_DFPU }, 116 { "l.d", "T,i16(s)", MIPS_OP(0x35), MA_MIPS2, MO_DFPU }, 117 { "l.d", "T,(s)", MIPS_OP(0x35), MA_MIPS2, MO_DFPU }, 118 { "ulv.q", "vt,i16(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_IMMALIGNED }, 119 { "ulv.q", "vt,(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED }, 120 { "lvl.q", "vt,i16(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED }, 121 { "lvl.q", "vt,(s)", MIPS_OP(0x35), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT }, 122 { "lvr.q", "vt,i16(s)", MIPS_OP(0x35)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED }, 123 { "lvr.q", "vt,(s)", MIPS_OP(0x35)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT }, 124 { "lv.q", "vt,i16(s)", MIPS_OP(0x36), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED }, 125 { "lv.q", "vt,(s)", MIPS_OP(0x36), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT }, 126 { "lqc2", "Vt,i16(s)", MIPS_OP(0x36), MA_PS2, MO_DELAYRT }, 127 { "ld", "t,i16(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 128 { "ld", "t,(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 129 { "sc", "t,i16(s)", MIPS_OP(0x38), MA_MIPS2, 0 }, 130 { "sc", "t,(s)", MIPS_OP(0x38), MA_MIPS2, 0 }, 131 { "swc1", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU }, 132 { "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU }, 133 { "s.s", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU }, 134 { "s.s", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU }, 135 { "swc2", "gt,i16(s)", MIPS_OP(0x3A), MA_PSX, 0 }, 136 { "swc2", "gt,(s)", MIPS_OP(0x3A), MA_PSX, 0 }, 137 { "sv.s", "vt,i16(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED }, 138 { "sv.s", "vt,(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED }, 139 { "scd", "t,i16(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 140 { "scd", "t,(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 141 { "sdc1", "T,i16(s)", MIPS_OP(0x3D), MA_MIPS2, MO_DFPU }, 142 { "sdc1", "T,(s)", MIPS_OP(0x3D), MA_MIPS2, MO_DFPU }, 143 { "s.d", "T,i16(s)", MIPS_OP(0x3D), MA_MIPS2, MO_DFPU }, 144 { "s.d", "T,(s)", MIPS_OP(0x3D), MA_MIPS2, MO_DFPU }, 145 { "usv.q", "vt,i16(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_IMMALIGNED }, 146 { "usv.q", "vt,(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED }, 147 { "svl.q", "vt,i16(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED }, 148 { "svl.q", "vt,(s)", MIPS_OP(0x3D), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT }, 149 { "svr.q", "vt,i16(s)", MIPS_OP(0x3D)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED }, 150 { "svr.q", "vt,(s)", MIPS_OP(0x3D)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT }, 151 { "sv.q", "vt,i16(s),w", MIPS_OP(0x3E)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED }, 152 { "sv.q", "vt,(s),w", MIPS_OP(0x3E)|0x02, MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT }, 153 { "sv.q", "vt,i16(s)", MIPS_OP(0x3E), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT|MO_IMMALIGNED }, 154 { "sv.q", "vt,(s)", MIPS_OP(0x3E), MA_PSP, MO_VFPU_QUAD|MO_VFPU_MIXED|MO_VFPU_6BIT }, 155 { "sqc2", "Vt,i16(s)", MIPS_OP(0x3E), MA_PS2, MO_DELAYRT }, 156 { "sd", "t,i16(s)", MIPS_OP(0x3F), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 157 { "sd", "t,(s)", MIPS_OP(0x3F), MA_MIPS3, MO_64BIT|MO_DELAYRT }, 158 159 // 31---------26------------------------------------------5--------0 160 // |= SPECIAL| | function| 161 // ------6----------------------------------------------------6----- 162 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 163 // 000 | SLL | --- | SRL*1 | SRA | SLLV | --- | SRLV*2| SRAV | 00..07 164 // 001 | JR | JALR | MOVZ | MOVN |SYSCALL| BREAK | --- | SYNC | 08..0F 165 // 010 | MFHI | MTHI | MFLO | MTLO | DSLLV | --- | *3 | *4 | 10..17 166 // 011 | MULT | MULTU | DIV | DIVU | MADD | MADDU | ---- | ----- | 18..1F 167 // 100 | ADD | ADDU | SUB | SUBU | AND | OR | XOR | NOR | 20..27 168 // 101 | mfsa | mtsa | SLT | SLTU | *5 | *6 | *7 | *8 | 28..2F 169 // 110 | TGE | TGEU | TLT | TLTU | TEQ | --- | TNE | --- | 30..37 170 // 111 | dsll | --- | dsrl | dsra |dsll32 | --- |dsrl32 |dsra32 | 38..3F 171 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 172 // *1: rotr when rs = 1 (PSP only) *2: rotrv when sa = 1 (PSP only) 173 // *3: dsrlv on PS2, clz on PSP *4: dsrav on PS2, clo on PSP 174 // *5: dadd on PS2, max on PSP *6: daddu on PS2, min on PSP 175 // *7: dsub on PS2, msub on PSP *8: dsubu on PS2, msubu on PSP 176 { "sll", "d,t,i5", MIPS_SPECIAL(0x00), MA_MIPS1, 0 }, 177 { "sll", "d,i5", MIPS_SPECIAL(0x00), MA_MIPS1, MO_RDT }, 178 { "nop", "", MIPS_SPECIAL(0x00), MA_MIPS1, 0 }, 179 { "srl", "d,t,i5", MIPS_SPECIAL(0x02), MA_MIPS1, 0 }, 180 { "srl", "d,i5", MIPS_SPECIAL(0x02), MA_MIPS1, MO_RDT }, 181 { "rotr", "d,t,i5", MIPS_SPECIAL(0x02)|MIPS_RS(1), MA_PSP, 0 }, 182 { "rotr", "d,i5", MIPS_SPECIAL(0x02)|MIPS_RS(1), MA_PSP, MO_RDT }, 183 { "sra", "d,t,i5", MIPS_SPECIAL(0x03), MA_MIPS1, 0 }, 184 { "sra", "d,i5", MIPS_SPECIAL(0x03), MA_MIPS1, MO_RDT }, 185 { "sllv", "d,t,s", MIPS_SPECIAL(0x04), MA_MIPS1, 0 }, 186 { "sllv", "d,s", MIPS_SPECIAL(0x04), MA_MIPS1, MO_RDT }, 187 { "srlv", "d,t,s", MIPS_SPECIAL(0x06), MA_MIPS1, 0 }, 188 { "srlv", "d,s", MIPS_SPECIAL(0x06), MA_MIPS1, MO_RDT }, 189 { "rotrv", "d,t,s", MIPS_SPECIAL(0x06)|MIPS_SA(1), MA_PSP, 0 }, 190 { "rotrv", "d,s", MIPS_SPECIAL(0x06)|MIPS_SA(1), MA_PSP, MO_RDT }, 191 { "srav", "d,t,s", MIPS_SPECIAL(0x07), MA_MIPS1, 0 }, 192 { "srav", "d,s", MIPS_SPECIAL(0x07), MA_MIPS1, MO_RDT }, 193 { "jr", "s", MIPS_SPECIAL(0x08), MA_MIPS1, MO_DELAY|MO_NODELAYSLOT }, 194 { "jalr", "s,d", MIPS_SPECIAL(0x09), MA_MIPS1, MO_DELAY|MO_NODELAYSLOT }, 195 { "jalr", "s", MIPS_SPECIAL(0x09)|MIPS_RD(31), MA_MIPS1, MO_DELAY|MO_NODELAYSLOT }, 196 { "movz", "d,s,t", MIPS_SPECIAL(0x0A), MA_MIPS4|MA_PS2|MA_PSP, 0 }, 197 { "movn", "d,s,t", MIPS_SPECIAL(0x0B), MA_MIPS4|MA_PS2|MA_PSP, 0 }, 198 { "syscall","i20", MIPS_SPECIAL(0x0C), MA_MIPS1, MO_NODELAYSLOT }, 199 { "syscall","", MIPS_SPECIAL(0x0C), MA_MIPS1, MO_NODELAYSLOT }, 200 { "break", "i20", MIPS_SPECIAL(0x0D), MA_MIPS1, MO_NODELAYSLOT }, 201 { "break", "", MIPS_SPECIAL(0x0D), MA_MIPS1, MO_NODELAYSLOT }, 202 { "sync", "", MIPS_SPECIAL(0x0F), MA_MIPS2, 0 }, 203 { "mfhi", "d", MIPS_SPECIAL(0x10), MA_MIPS1, 0 }, 204 { "mthi", "s", MIPS_SPECIAL(0x11), MA_MIPS1, 0 }, 205 { "mflo", "d", MIPS_SPECIAL(0x12), MA_MIPS1, 0 }, 206 { "mtlo", "s", MIPS_SPECIAL(0x13), MA_MIPS1, 0 }, 207 { "dsllv", "d,t,s", MIPS_SPECIAL(0x14), MA_MIPS3, MO_64BIT }, 208 { "dsllv", "d,s", MIPS_SPECIAL(0x14), MA_MIPS3, MO_64BIT|MO_RDT }, 209 { "dsrlv", "d,t,s", MIPS_SPECIAL(0x16), MA_MIPS3, MO_64BIT }, 210 { "dsrlv", "d,s", MIPS_SPECIAL(0x16), MA_MIPS3, MO_64BIT|MO_RDT }, 211 { "clz", "d,s", MIPS_SPECIAL(0x16), MA_PSP, 0 }, 212 { "dsrav", "d,t,s", MIPS_SPECIAL(0x17), MA_MIPS3, MO_64BIT }, 213 { "dsrav", "d,s", MIPS_SPECIAL(0x17), MA_MIPS3, MO_64BIT|MO_RDT }, 214 { "clo", "d,s", MIPS_SPECIAL(0x17), MA_PSP, 0 }, 215 { "mult", "d,s,t", MIPS_SPECIAL(0x18), MA_PS2, 0 }, 216 { "multu", "d,s,t", MIPS_SPECIAL(0x19), MA_PS2, 0 }, 217 { "mult", "s,t", MIPS_SPECIAL(0x18), MA_MIPS1|MA_EXRSP, 0 }, 218 { "mult", "r\x0,s,t", MIPS_SPECIAL(0x18), MA_MIPS1|MA_EXRSP, 0 }, 219 { "multu", "s,t", MIPS_SPECIAL(0x19), MA_MIPS1|MA_EXRSP, 0 }, 220 { "multu", "r\x0,s,t", MIPS_SPECIAL(0x19), MA_MIPS1|MA_EXRSP, 0 }, 221 { "div", "s,t", MIPS_SPECIAL(0x1A), MA_MIPS1|MA_EXRSP, 0 }, 222 { "div", "r\x0,s,t", MIPS_SPECIAL(0x1A), MA_MIPS1|MA_EXRSP, 0 }, 223 { "divu", "s,t", MIPS_SPECIAL(0x1B), MA_MIPS1|MA_EXRSP, 0 }, 224 { "divu", "r\x0,s,t", MIPS_SPECIAL(0x1B), MA_MIPS1|MA_EXRSP, 0 }, 225 { "dmult", "s,t", MIPS_SPECIAL(0x1C), MA_MIPS3|MA_EXPS2, MO_64BIT }, 226 { "dmult", "r\x0,s,t", MIPS_SPECIAL(0x1C), MA_MIPS3|MA_EXPS2, MO_64BIT }, 227 { "madd", "s,t", MIPS_SPECIAL(0x1C), MA_PSP, 0 }, 228 { "dmultu", "s,t", MIPS_SPECIAL(0x1D), MA_MIPS3|MA_EXPS2, MO_64BIT }, 229 { "dmultu", "r\x0,s,t", MIPS_SPECIAL(0x1D), MA_MIPS3|MA_EXPS2, MO_64BIT }, 230 { "maddu", "s,t", MIPS_SPECIAL(0x1D), MA_PSP, 0 }, 231 { "ddiv", "s,t", MIPS_SPECIAL(0x1E), MA_MIPS3|MA_EXPS2, MO_64BIT }, 232 { "ddiv", "r\x0,s,t", MIPS_SPECIAL(0x1E), MA_MIPS3|MA_EXPS2, MO_64BIT }, 233 { "ddivu", "s,t", MIPS_SPECIAL(0x1F), MA_MIPS3|MA_EXPS2, MO_64BIT }, 234 { "ddivu", "r\x0,s,t", MIPS_SPECIAL(0x1F), MA_MIPS3|MA_EXPS2, MO_64BIT }, 235 { "add", "d,s,t", MIPS_SPECIAL(0x20), MA_MIPS1, 0 }, 236 { "add", "s,t", MIPS_SPECIAL(0x20), MA_MIPS1, MO_RSD }, 237 { "addu", "d,s,t", MIPS_SPECIAL(0x21), MA_MIPS1, 0 }, 238 { "addu", "s,t", MIPS_SPECIAL(0x21), MA_MIPS1, MO_RSD }, 239 { "move", "d,s", MIPS_SPECIAL(0x21), MA_MIPS1, 0 }, 240 { "clear", "d", MIPS_SPECIAL(0x21), MA_MIPS1, 0 }, 241 { "sub", "d,s,t", MIPS_SPECIAL(0x22), MA_MIPS1, 0 }, 242 { "sub", "s,t", MIPS_SPECIAL(0x22), MA_MIPS1, MO_RSD }, 243 { "neg", "d,t", MIPS_SPECIAL(0x22), MA_MIPS1, 0 }, 244 { "subu", "d,s,t", MIPS_SPECIAL(0x23), MA_MIPS1, 0 }, 245 { "subu", "s,t", MIPS_SPECIAL(0x23), MA_MIPS1, MO_RSD }, 246 { "negu", "d,t", MIPS_SPECIAL(0x23), MA_MIPS1, 0 }, 247 { "and", "d,s,t", MIPS_SPECIAL(0x24), MA_MIPS1, 0 }, 248 { "and", "s,t", MIPS_SPECIAL(0x24), MA_MIPS1, MO_RSD }, 249 { "or", "d,s,t", MIPS_SPECIAL(0x25), MA_MIPS1, 0 }, 250 { "or", "s,t", MIPS_SPECIAL(0x25), MA_MIPS1, MO_RSD }, 251 { "xor", "d,s,t", MIPS_SPECIAL(0x26), MA_MIPS1, 0 }, 252 { "eor", "d,s,t", MIPS_SPECIAL(0x26), MA_MIPS1, 0 }, 253 { "xor", "s,t", MIPS_SPECIAL(0x26), MA_MIPS1, MO_RSD }, 254 { "eor", "s,t", MIPS_SPECIAL(0x26), MA_MIPS1, MO_RSD }, 255 { "nor", "d,s,t", MIPS_SPECIAL(0x27), MA_MIPS1, 0 }, 256 { "nor", "s,t", MIPS_SPECIAL(0x27), MA_MIPS1, MO_RSD }, 257 { "not", "d,s", MIPS_SPECIAL(0x27), MA_MIPS1, 0 }, 258 { "mfsa", "d", MIPS_SPECIAL(0x28), MA_PS2, 0 }, 259 { "mtsa", "s", MIPS_SPECIAL(0x29), MA_PS2, 0 }, 260 { "slt", "d,s,t", MIPS_SPECIAL(0x2A), MA_MIPS1, 0 }, 261 { "slt", "s,t", MIPS_SPECIAL(0x2A), MA_MIPS1, MO_RSD}, 262 { "sgt", "d,t,s", MIPS_SPECIAL(0x2A), MA_MIPS1, 0 }, 263 { "sgt", "d,s", MIPS_SPECIAL(0x2A), MA_MIPS1, MO_RDT}, 264 { "sltu", "d,s,t", MIPS_SPECIAL(0x2B), MA_MIPS1, 0 }, 265 { "sltu", "s,t", MIPS_SPECIAL(0x2B), MA_MIPS1, MO_RSD }, 266 { "sgtu", "d,t,s", MIPS_SPECIAL(0x2B), MA_MIPS1, 0 }, 267 { "sgtu", "d,s", MIPS_SPECIAL(0x2B), MA_MIPS1, MO_RDT}, 268 { "dadd", "d,s,t", MIPS_SPECIAL(0x2C), MA_MIPS3, MO_64BIT }, 269 { "dadd", "s,t", MIPS_SPECIAL(0x2C), MA_MIPS3, MO_64BIT|MO_RSD }, 270 { "max", "d,s,t", MIPS_SPECIAL(0x2C), MA_PSP, 0 }, 271 { "daddu", "d,s,t", MIPS_SPECIAL(0x2D), MA_MIPS3, MO_64BIT }, 272 { "daddu", "s,t", MIPS_SPECIAL(0x2D), MA_MIPS3, MO_64BIT|MO_RSD }, 273 { "dmove", "d,s", MIPS_SPECIAL(0x2D), MA_MIPS3, MO_64BIT }, 274 { "min", "d,s,t", MIPS_SPECIAL(0x2D), MA_PSP, 0 }, 275 { "dsub", "d,s,t", MIPS_SPECIAL(0x2E), MA_MIPS3, MO_64BIT }, 276 { "dsub", "s,t", MIPS_SPECIAL(0x2E), MA_MIPS3, MO_64BIT|MO_RSD }, 277 { "dneg", "d,t", MIPS_SPECIAL(0x2E), MA_MIPS3, MO_64BIT }, 278 { "msub", "s,t", MIPS_SPECIAL(0x2E), MA_PSP, 0 }, 279 { "dsubu", "d,s,t", MIPS_SPECIAL(0x2F), MA_MIPS3, MO_64BIT }, 280 { "dsubu", "s,t", MIPS_SPECIAL(0x2F), MA_MIPS3, MO_64BIT|MO_RSD }, 281 { "dnegu", "d,t", MIPS_SPECIAL(0x2F), MA_MIPS3, MO_64BIT }, 282 { "msubu", "s,t", MIPS_SPECIAL(0x2F), MA_PSP, 0 }, 283 { "tge", "s,t,i10", MIPS_SPECIAL(0x30), MA_MIPS2, 0 }, 284 { "tge", "s,t", MIPS_SPECIAL(0x30), MA_MIPS2, 0 }, 285 { "tgeu", "s,t,i10", MIPS_SPECIAL(0x31), MA_MIPS2, 0 }, 286 { "tgeu", "s,t", MIPS_SPECIAL(0x31), MA_MIPS2, 0 }, 287 { "tlt", "s,t,i10", MIPS_SPECIAL(0x32), MA_MIPS2, 0 }, 288 { "tlt", "s,t", MIPS_SPECIAL(0x32), MA_MIPS2, 0 }, 289 { "tltu", "s,t,i10", MIPS_SPECIAL(0x33), MA_MIPS2, 0 }, 290 { "tltu", "s,t", MIPS_SPECIAL(0x33), MA_MIPS2, 0 }, 291 { "teq", "s,t,i10", MIPS_SPECIAL(0x34), MA_MIPS2, 0 }, 292 { "teq", "s,t", MIPS_SPECIAL(0x34), MA_MIPS2, 0 }, 293 { "tne", "s,t,i10", MIPS_SPECIAL(0x36), MA_MIPS2, 0 }, 294 { "tne", "s,t", MIPS_SPECIAL(0x36), MA_MIPS2, 0 }, 295 { "dsll", "d,t,i5", MIPS_SPECIAL(0x38), MA_MIPS3, MO_64BIT }, 296 { "dsll", "d,i5", MIPS_SPECIAL(0x38), MA_MIPS3, MO_64BIT|MO_RDT }, 297 { "dsrl", "d,t,i5", MIPS_SPECIAL(0x3A), MA_MIPS3, MO_64BIT }, 298 { "dsrl", "d,i5", MIPS_SPECIAL(0x3A), MA_MIPS3, MO_64BIT|MO_RDT }, 299 { "dsra", "d,t,i5", MIPS_SPECIAL(0x3B), MA_MIPS3, MO_64BIT }, 300 { "dsra", "d,i5", MIPS_SPECIAL(0x3B), MA_MIPS3, MO_64BIT|MO_RDT }, 301 { "dsll32", "d,t,i5", MIPS_SPECIAL(0x3C), MA_MIPS3, MO_64BIT }, 302 { "dsll32", "d,i5", MIPS_SPECIAL(0x3C), MA_MIPS3, MO_64BIT|MO_RDT }, 303 { "dsrl32", "d,t,i5", MIPS_SPECIAL(0x3E), MA_MIPS3, MO_64BIT }, 304 { "dsrl32", "d,i5", MIPS_SPECIAL(0x3E), MA_MIPS3, MO_64BIT|MO_RDT }, 305 { "dsra32", "d,t,i5", MIPS_SPECIAL(0x3F), MA_MIPS3, MO_64BIT }, 306 { "dsra32", "d,i5", MIPS_SPECIAL(0x3F), MA_MIPS3, MO_64BIT|MO_RDT }, 307 308 // REGIMM: encoded by the rt field when opcode field = REGIMM. 309 // 31---------26----------20-------16------------------------------0 310 // |= REGIMM| | rt | | 311 // ------6---------------------5------------------------------------ 312 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 313 // 00 | BLTZ | BGEZ | BLTZL | BGEZL | --- | --- | --- | --- | 00-07 314 // 01 | tgei | tgeiu | tlti | tltiu | teqi | --- | tnei | --- | 08-0F 315 // 10 | BLTZAL| BGEZAL|BLTZALL|BGEZALL| --- | --- | --- | --- | 10-17 316 // 11 | mtsab | mtsah | --- | --- | --- | --- | --- | --- | 18-1F 317 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 318 { "bltz", "s,i16", MIPS_REGIMM(0x00), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 319 { "bgez", "s,i16", MIPS_REGIMM(0x01), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 320 { "bltzl", "s,i16", MIPS_REGIMM(0x02), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 321 { "bgezl", "s,i16", MIPS_REGIMM(0x03), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 322 { "tgei", "s,i16", MIPS_REGIMM(0x08), MA_MIPS2, 0 }, 323 { "tgeiu", "s,i16", MIPS_REGIMM(0x09), MA_MIPS2, 0 }, 324 { "tlti", "s,i16", MIPS_REGIMM(0x0A), MA_MIPS2, 0 }, 325 { "tltiu", "s,i16", MIPS_REGIMM(0x0B), MA_MIPS2, 0 }, 326 { "teqi", "s,i16", MIPS_REGIMM(0x0C), MA_MIPS2, 0 }, 327 { "tnei", "s,i16", MIPS_REGIMM(0x0E), MA_MIPS2, 0 }, 328 { "bltzal", "s,i16", MIPS_REGIMM(0x10), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 329 { "bgezal", "s,i16", MIPS_REGIMM(0x11), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 330 { "bal", "i16", MIPS_REGIMM(0x11), MA_MIPS1, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 331 { "bltzall","s,i16", MIPS_REGIMM(0x12), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 332 { "bgezall","s,i16", MIPS_REGIMM(0x13), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 333 { "mtsab", "s,i16", MIPS_REGIMM(0x18), MA_PS2, 0 }, 334 { "mtsah", "s,i16", MIPS_REGIMM(0x19), MA_PS2, 0 }, 335 336 // 31---------26---------21----------------------------------------0 337 // |= COP0| rs | | 338 // -----6-------5--------------------------------------------------- 339 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 340 // 00 | MFC0 | DMFC0 | --- | --- | MTC0 | DMTC0 | --- | --- | 00..07 341 // 01 | --- | --- | --- | --- | --- | --- | --- | --- | 08..0F 342 // 10 |FUNCT* | --- | --- | --- | --- | --- | --- | --- | 10..17 343 // 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 344 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 345 { "mfc0", "t,z", MIPS_COP0(0x00), MA_MIPS1|MA_EXRSP, 0 }, 346 { "mfc0", "t,Rz", MIPS_COP0(0x00), MA_RSP, 0 }, 347 { "dmfc0", "t,z", MIPS_COP0(0x01), MA_MIPS3, MO_64BIT }, 348 { "mtc0", "t,z", MIPS_COP0(0x04), MA_MIPS1|MA_EXRSP, 0 }, 349 { "mtc0", "t,Rz", MIPS_COP0(0x04), MA_RSP, 0 }, 350 { "dmtc0", "t,z", MIPS_COP0(0x05), MA_MIPS3, MO_64BIT }, 351 352 // 31--------------------21-------------------------------5--------0 353 // |= COP0FUNCT| | function| 354 // -----11----------------------------------------------------6----- 355 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 356 // 000 | --- | TLBR | TLBWI | --- | --- | --- | TLBWR | --- | 00..07 357 // 001 | TLBP | --- | --- | --- | --- | --- | --- | --- | 08..0F 358 // 010 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17 359 // 011 | ERET | --- | --- | --- | --- | --- | --- | --- | 18..1F 360 // 100 | --- | --- | --- | --- | --- | --- | --- | --- | 20..27 361 // 101 | --- | --- | --- | --- | --- | --- | --- | --- | 28..2F 362 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 30..37 363 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 38..3F 364 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 365 { "tlbr", "", MIPS_COP0FUNCT(0x01), MA_MIPS3, 0 }, 366 { "tlbwi", "", MIPS_COP0FUNCT(0x02), MA_MIPS3, 0 }, 367 { "tlbwr", "", MIPS_COP0FUNCT(0x06), MA_MIPS3, 0 }, 368 { "tlbp", "", MIPS_COP0FUNCT(0x08), MA_MIPS3, 0 }, 369 { "eret", "", MIPS_COP0FUNCT(0x18), MA_MIPS3, 0 }, 370 371 // 31---------26---------21----------------------------------------0 372 // |= COP1| rs | | 373 // -----6-------5--------------------------------------------------- 374 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 375 // 00 | MFC1 | DMFC1 | CFC1 | --- | MTC1 | DMTC1 | CTC1 | --- | 00..07 376 // 01 | BC* | --- | --- | --- | --- | --- | --- | --- | 08..0F 377 // 10 | S* | --- | --- | --- | W* | --- | --- | --- | 10..17 378 // 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 379 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 380 381 { "mfc1", "t,S", MIPS_COP1(0x00), MA_MIPS1, MO_FPU }, 382 { "dmfc1", "t,S", MIPS_COP1(0x01), MA_MIPS3, MO_DFPU|MO_64BIT }, 383 { "cfc1", "t,f", MIPS_COP1(0x02), MA_MIPS1, MO_FPU }, 384 { "mtc1", "t,S", MIPS_COP1(0x04), MA_MIPS1, MO_FPU }, 385 { "dmtc1", "t,S", MIPS_COP1(0x05), MA_MIPS3, MO_DFPU|MO_64BIT }, 386 { "ctc1", "t,f", MIPS_COP1(0x06), MA_MIPS1, MO_FPU }, 387 388 // 31---------26----------20-------16------------------------------0 389 // |= COP1BC| | rt | | 390 // ------11--------------5------------------------------------------ 391 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 392 // 00 | BC1F | BC1T | BC1FL | BC1TL | --- | --- | --- | --- | 00..07 393 // 01 | --- | --- | --- | --- | --- | --- | --- | --- | 08..0F 394 // 10 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17 395 // 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 396 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 397 { "bc1f", "i16", MIPS_COP1BC(0x00), MA_MIPS1, MO_FPU|MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 398 { "bc1t", "i16", MIPS_COP1BC(0x01), MA_MIPS1, MO_FPU|MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 399 { "bc1fl", "i16", MIPS_COP1BC(0x02), MA_MIPS2, MO_FPU|MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 400 { "bc1tl", "i16", MIPS_COP1BC(0x03), MA_MIPS2, MO_FPU|MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 401 402 // 31--------------------21-------------------------------5--------0 403 // |= COP1S| | function| 404 // -----11----------------------------------------------------6----- 405 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 406 // 000 | add | sub | mul | div | sqrt | abs | mov | neg | 00..07 407 // 001 |round.l|trunc.l|ceil.l |floor.l|round.w|trunc.w|ceil.w |floor.w| 08..0F 408 // 010 | --- | --- | --- | --- | --- | --- | rsqrt | --- | 10..17 409 // 011 | adda | suba | mula | --- | madd | msub | madda | msuba | 18..1F 410 // 100 | --- | cvt.d | --- | --- | cvt.w | cvt.l | --- | --- | 20..27 411 // 101 | max | min | --- | --- | --- | --- | --- | --- | 28..2F 412 // 110 | c.f | c.un | c.eq | c.ueq |c.(o)lt| c.ult |c.(o)le| c.ule | 30..37 413 // 110 | c.sf | c.ngle| c.seq | c.ngl | c.lt | c.nge | c.le | c.ngt | 38..3F 414 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 415 { "add.s", "D,S,T", MIPS_COP1S(0x00), MA_MIPS1, MO_FPU }, 416 { "add.s", "S,T", MIPS_COP1S(0x00), MA_MIPS1, MO_FPU|MO_FRSD }, 417 { "sub.s", "D,S,T", MIPS_COP1S(0x01), MA_MIPS1, MO_FPU }, 418 { "sub.s", "S,T", MIPS_COP1S(0x01), MA_MIPS1, MO_FPU|MO_FRSD }, 419 { "mul.s", "D,S,T", MIPS_COP1S(0x02), MA_MIPS1, MO_FPU }, 420 { "mul.s", "S,T", MIPS_COP1S(0x02), MA_MIPS1, MO_FPU|MO_FRSD }, 421 { "div.s", "D,S,T", MIPS_COP1S(0x03), MA_MIPS1, MO_FPU }, 422 { "div.s", "S,T", MIPS_COP1S(0x03), MA_MIPS1, MO_FPU|MO_FRSD }, 423 { "sqrt.s", "D,S", MIPS_COP1S(0x04), MA_MIPS2, MO_FPU }, 424 { "abs.s", "D,S", MIPS_COP1S(0x05), MA_MIPS1, MO_FPU }, 425 { "mov.s", "D,S", MIPS_COP1S(0x06), MA_MIPS1, MO_FPU }, 426 { "neg.s", "D,S", MIPS_COP1S(0x07), MA_MIPS1, MO_FPU }, 427 { "round.l.s", "D,S", MIPS_COP1S(0x08), MA_MIPS3, MO_DFPU }, 428 { "trunc.l.s", "D,S", MIPS_COP1S(0x09), MA_MIPS3, MO_DFPU }, 429 { "ceil.l.s", "D,S", MIPS_COP1S(0x0A), MA_MIPS3, MO_DFPU }, 430 { "floor.l.s", "D,S", MIPS_COP1S(0x0B), MA_MIPS3, MO_DFPU }, 431 { "round.w.s", "D,S", MIPS_COP1S(0x0C), MA_MIPS2|MA_EXPS2, MO_FPU }, 432 { "trunc.w.s", "D,S", MIPS_COP1S(0x0D), MA_MIPS1|MA_EXPS2, MO_FPU }, 433 { "ceil.w.s", "D,S", MIPS_COP1S(0x0E), MA_MIPS2|MA_EXPS2, MO_FPU }, 434 { "floor.w.s", "D,S", MIPS_COP1S(0x0F), MA_MIPS2|MA_EXPS2, MO_FPU }, 435 { "rsqrt.w.s", "D,S", MIPS_COP1S(0x16), MA_PS2, 0 }, 436 { "adda.s", "S,T", MIPS_COP1S(0x18), MA_PS2, 0 }, 437 { "suba.s", "S,T", MIPS_COP1S(0x19), MA_PS2, 0 }, 438 { "mula.s", "S,T", MIPS_COP1S(0x1A), MA_PS2, 0 }, 439 { "madd.s", "D,S,T", MIPS_COP1S(0x1C), MA_PS2, 0 }, 440 { "madd.s", "S,T", MIPS_COP1S(0x1C), MA_PS2, MO_FRSD }, 441 { "msub.s", "D,S,T", MIPS_COP1S(0x1D), MA_PS2, 0 }, 442 { "msub.s", "S,T", MIPS_COP1S(0x1D), MA_PS2, MO_FRSD }, 443 { "madda.s", "S,T", MIPS_COP1S(0x1E), MA_PS2, 0 }, 444 { "msuba.s", "S,T", MIPS_COP1S(0x1F), MA_PS2, 0 }, 445 { "cvt.d.s", "D,S", MIPS_COP1S(0x21), MA_MIPS1, MO_DFPU }, 446 { "cvt.w.s", "D,S", MIPS_COP1S(0x24), MA_MIPS1, MO_FPU }, 447 { "cvt.l.s", "D,S", MIPS_COP1S(0x25), MA_MIPS3, MO_DFPU }, 448 { "max.s", "D,S,T", MIPS_COP1S(0x28), MA_PS2, 0 }, 449 { "min.s", "D,S,T", MIPS_COP1S(0x29), MA_PS2, 0 }, 450 { "c.f.s", "S,T", MIPS_COP1S(0x30), MA_MIPS1, MO_FPU }, 451 { "c.un.s", "S,T", MIPS_COP1S(0x31), MA_MIPS1|MA_EXPS2, MO_FPU }, 452 { "c.eq.s", "S,T", MIPS_COP1S(0x32), MA_MIPS1, MO_FPU }, 453 { "c.ueq.s", "S,T", MIPS_COP1S(0x33), MA_MIPS1|MA_EXPS2, MO_FPU }, 454 { "c.olt.s", "S,T", MIPS_COP1S(0x34), MA_MIPS1|MA_EXPS2, MO_FPU }, 455 { "c.lt.s", "S,T", MIPS_COP1S(0x34), MA_PS2, 0 }, 456 { "c.ult.s", "S,T", MIPS_COP1S(0x35), MA_MIPS1|MA_EXPS2, MO_FPU }, 457 { "c.ole.s", "S,T", MIPS_COP1S(0x36), MA_MIPS1|MA_EXPS2, MO_FPU }, 458 { "c.le.s", "S,T", MIPS_COP1S(0x36), MA_PS2, 0 }, 459 { "c.ule.s", "S,T", MIPS_COP1S(0x37), MA_MIPS1|MA_EXPS2, MO_FPU }, 460 { "c.sf.s", "S,T", MIPS_COP1S(0x38), MA_MIPS1|MA_EXPS2, MO_FPU }, 461 { "c.ngle.s", "S,T", MIPS_COP1S(0x39), MA_MIPS1|MA_EXPS2, MO_FPU }, 462 { "c.seq.s", "S,T", MIPS_COP1S(0x3A), MA_MIPS1|MA_EXPS2, MO_FPU }, 463 { "c.ngl.s", "S,T", MIPS_COP1S(0x3B), MA_MIPS1|MA_EXPS2, MO_FPU }, 464 { "c.lt.s", "S,T", MIPS_COP1S(0x3C), MA_MIPS1|MA_EXPS2, MO_FPU }, 465 { "c.nge.s", "S,T", MIPS_COP1S(0x3D), MA_MIPS1|MA_EXPS2, MO_FPU }, 466 { "c.le.s", "S,T", MIPS_COP1S(0x3E), MA_MIPS1|MA_EXPS2, MO_FPU }, 467 { "c.ngt.s", "S,T", MIPS_COP1S(0x3F), MA_MIPS1|MA_EXPS2, MO_FPU }, 468 469 // 31--------------------21-------------------------------5--------0 470 // |= COP1D| | function| 471 // -----11----------------------------------------------------6----- 472 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 473 // 000 | add | sub | mul | div | sqrt | abs | mov | neg | 00..07 474 // 001 |round.l|trunc.l|ceil.l |floor.l|round.w|trunc.w|ceil.w |floor.w| 08..0F 475 // 010 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17 476 // 011 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 477 // 100 | cvt.s | --- | --- | --- | cvt.w | cvt.l | --- | --- | 20..27 478 // 101 | --- | --- | --- | --- | --- | --- | --- | --- | 28..2F 479 // 110 | c.f | c.un | c.eq | c.ueq | c.olt | c.ult | c.ole | c.ule | 30..37 480 // 110 | c.sf | c.ngle| c.seq | c.ngl | c.lt | c.nge | c.le | c.ngt | 38..3F 481 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 482 { "add.d", "D,S,T", MIPS_COP1D(0x00), MA_MIPS1, MO_DFPU }, 483 { "add.d", "S,T", MIPS_COP1D(0x00), MA_MIPS1, MO_DFPU|MO_FRSD }, 484 { "sub.d", "D,S,T", MIPS_COP1D(0x01), MA_MIPS1, MO_DFPU }, 485 { "sub.d", "S,T", MIPS_COP1D(0x01), MA_MIPS1, MO_DFPU|MO_FRSD }, 486 { "mul.d", "D,S,T", MIPS_COP1D(0x02), MA_MIPS1, MO_DFPU }, 487 { "mul.d", "S,T", MIPS_COP1D(0x02), MA_MIPS1, MO_DFPU|MO_FRSD }, 488 { "div.d", "D,S,T", MIPS_COP1D(0x03), MA_MIPS1, MO_DFPU }, 489 { "div.d", "S,T", MIPS_COP1D(0x03), MA_MIPS1, MO_DFPU|MO_FRSD }, 490 { "sqrt.d", "D,S", MIPS_COP1D(0x04), MA_MIPS2, MO_DFPU }, 491 { "abs.d", "D,S", MIPS_COP1D(0x05), MA_MIPS1, MO_DFPU }, 492 { "mov.d", "D,S", MIPS_COP1D(0x06), MA_MIPS1, MO_DFPU }, 493 { "neg.d", "D,S", MIPS_COP1D(0x07), MA_MIPS1, MO_DFPU }, 494 { "round.l.d", "D,S", MIPS_COP1D(0x08), MA_MIPS3, MO_DFPU }, 495 { "trunc.l.d", "D,S", MIPS_COP1D(0x09), MA_MIPS3, MO_DFPU }, 496 { "ceil.l.d", "D,S", MIPS_COP1D(0x0A), MA_MIPS3, MO_DFPU }, 497 { "floor.l.d", "D,S", MIPS_COP1D(0x0B), MA_MIPS3, MO_DFPU }, 498 { "round.w.d", "D,S", MIPS_COP1D(0x0C), MA_MIPS2, MO_DFPU }, 499 { "trunc.w.d", "D,S", MIPS_COP1D(0x0D), MA_MIPS1, MO_DFPU }, 500 { "ceil.w.d", "D,S", MIPS_COP1D(0x0E), MA_MIPS2, MO_DFPU }, 501 { "floor.w.d", "D,S", MIPS_COP1D(0x0F), MA_MIPS2, MO_DFPU }, 502 { "cvt.s.d", "D,S", MIPS_COP1D(0x20), MA_MIPS1, MO_DFPU }, 503 { "cvt.w.d", "D,S", MIPS_COP1D(0x24), MA_MIPS1, MO_DFPU }, 504 { "cvt.l.d", "D,S", MIPS_COP1D(0x25), MA_MIPS3, MO_DFPU }, 505 { "c.f.d", "S,T", MIPS_COP1D(0x30), MA_MIPS1, MO_DFPU }, 506 { "c.un.d", "S,T", MIPS_COP1D(0x31), MA_MIPS1, MO_DFPU }, 507 { "c.eq.d", "S,T", MIPS_COP1D(0x32), MA_MIPS1, MO_DFPU }, 508 { "c.ueq.d", "S,T", MIPS_COP1D(0x33), MA_MIPS1, MO_DFPU }, 509 { "c.olt.d", "S,T", MIPS_COP1D(0x34), MA_MIPS1, MO_DFPU }, 510 { "c.ult.d", "S,T", MIPS_COP1D(0x35), MA_MIPS1, MO_DFPU }, 511 { "c.ole.d", "S,T", MIPS_COP1D(0x36), MA_MIPS1, MO_DFPU }, 512 { "c.ule.d", "S,T", MIPS_COP1D(0x37), MA_MIPS1, MO_DFPU }, 513 { "c.sf.d", "S,T", MIPS_COP1D(0x38), MA_MIPS1, MO_DFPU }, 514 { "c.ngle.d", "S,T", MIPS_COP1D(0x39), MA_MIPS1, MO_DFPU }, 515 { "c.seq.d", "S,T", MIPS_COP1D(0x3A), MA_MIPS1, MO_DFPU }, 516 { "c.ngl.d", "S,T", MIPS_COP1D(0x3B), MA_MIPS1, MO_DFPU }, 517 { "c.lt.d", "S,T", MIPS_COP1D(0x3C), MA_MIPS1, MO_DFPU }, 518 { "c.nge.d", "S,T", MIPS_COP1D(0x3D), MA_MIPS1, MO_DFPU }, 519 { "c.le.d", "S,T", MIPS_COP1D(0x3E), MA_MIPS1, MO_DFPU }, 520 { "c.ngt.d", "S,T", MIPS_COP1D(0x3F), MA_MIPS1, MO_DFPU }, 521 522 // 31--------------------21-------------------------------5--------0 523 // |= COP1W| | function| 524 // -----11----------------------------------------------------6----- 525 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 526 // 000 | --- | --- | --- | --- | --- | --- | --- | --- | 00..07 527 // 001 | --- | --- | --- | --- | --- | --- | --- | --- | 08..0F 528 // 010 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17 529 // 011 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 530 // 100 | cvt.s | cvt.d | --- | --- | --- | --- | --- | --- | 20..27 531 // 101 | --- | --- | --- | --- | --- | --- | --- | --- | 28..2F 532 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 30..37 533 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 38..3F 534 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 535 { "cvt.s.w", "D,S", MIPS_COP1W(0x20), MA_MIPS1, MO_FPU }, 536 { "cvt.d.w", "D,S", MIPS_COP1W(0x21), MA_MIPS1, MO_DFPU }, 537 538 // 31--------------------21-------------------------------5--------0 539 // |= COP1L| | function| 540 // -----11----------------------------------------------------6----- 541 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 542 // 000 | --- | --- | --- | --- | --- | --- | --- | --- | 00..07 543 // 001 | --- | --- | --- | --- | --- | --- | --- | --- | 08..0F 544 // 010 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17 545 // 011 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 546 // 100 | cvt.s | cvt.d | --- | --- | --- | --- | --- | --- | 20..27 547 // 101 | --- | --- | --- | --- | --- | --- | --- | --- | 28..2F 548 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 30..37 549 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 38..3F 550 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 551 { "cvt.s.l", "D,S", MIPS_COP1L(0x20), MA_MIPS3, MO_DFPU }, 552 { "cvt.d.l", "D,S", MIPS_COP1L(0x21), MA_MIPS3, MO_DFPU }, 553 554 // 31---------26---------21----------------------------------------0 555 // |= COP2| rs | | 556 // -----6-------5--------------------------------------------------- 557 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 558 // 00 | MFC2 | --- | CFC2 | MFV | MTC2 | --- | CTC2 | MTV | 559 // 01 | BC* | --- | --- | --- | --- | --- | --- | --- | 560 // 10 | --- | --- | --- | --- | --- | --- | --- | --- | 561 // 11 | --- | --- | --- | --- | --- | --- | --- | --- | 562 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 563 564 { "mfc2", "t,gs", MIPS_COP2(0x00), MA_PSX, 0 }, 565 { "mfc2", "t,RsRo", MIPS_COP2(0x00), MA_RSP, 0 }, 566 { "cfc2", "t,gc", MIPS_COP2(0x02), MA_PSX, 0 }, 567 { "cfc2", "t,Rc", MIPS_COP2(0x02), MA_RSP, 0 }, 568 { "mtc2", "t,gs", MIPS_COP2(0x04), MA_PSX, 0 }, 569 { "mtc2", "t,RsRo", MIPS_COP2(0x04), MA_RSP, 0 }, 570 { "ctc2", "t,gc", MIPS_COP2(0x06), MA_PSX, 0 }, 571 { "ctc2", "t,Rc", MIPS_COP2(0x06), MA_RSP, 0 }, 572 // VVVVVV VVVVV ttttt -------- C DDDDDDD 573 { "mfv", "t,vd", MIPS_COP2(0x03), MA_PSP, MO_VFPU|MO_VFPU_SINGLE }, 574 { "mfvc", "t,vc", MIPS_COP2(0x03)|0x80, MA_PSP, MO_VFPU }, 575 { "mtv", "t,vd", MIPS_COP2(0x07), MA_PSP, MO_VFPU|MO_VFPU_SINGLE }, 576 { "mtvc", "t,vc", MIPS_COP2(0x07)|0x80, MA_PSP, MO_VFPU }, 577 578 579 // COP2BC: ? indicates any, * indicates all 580 // 31---------26----------20-------16------------------------------0 581 // |= COP2BC| | rt | | 582 // ------11---------5----------------------------------------------- 583 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 584 // 00 | BVFx | BVTx | BVFLx | BVTLx | BVFy | BVTy | BVFLy | BVTLy | 585 // 01 | BVFz | BVTz | BVFLz | BVTLz | BVFw | BVTw | BVFLw | BVTLw | 586 // 10 | BVF? | BVT? | BVFL? | BVTL? | BVF* | BVT* | BVFL* | BVTL* | 587 // 11 | --- | --- | --- | --- | --- | --- | --- | --- | 588 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 589 { "bvf", "jb,i16", MIPS_COP2BC(0x00), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 590 { "bvf.B", "i16", MIPS_COP2BC(0x00), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 591 { "bvt", "jb,i16", MIPS_COP2BC(0x01), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 592 { "bvt.B", "i16", MIPS_COP2BC(0x01), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 593 { "bvfl", "jb,i16", MIPS_COP2BC(0x02), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 594 { "bvfl.B", "i16", MIPS_COP2BC(0x02), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 595 { "bvtl", "jb,i16", MIPS_COP2BC(0x03), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 596 { "bvtl.B", "i16", MIPS_COP2BC(0x03), MA_PSP, MO_IPCR|MO_DELAY|MO_NODELAYSLOT }, 597 598 // 31---------26-----23--------------------------------------------0 599 // |= VFPU0| VOP | | 600 // ------6--------3------------------------------------------------- 601 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| 602 // 000 | VADD | VSUB | VSBN | --- | --- | --- | --- | VDIV | 00..07 603 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 604 { "vadd.S", "vd,vs,vt", MIPS_VFPU0(0x00), MA_PSP, MO_VFPU }, 605 { "vsub.S", "vd,vs,vt", MIPS_VFPU0(0x01), MA_PSP, MO_VFPU }, 606 { "vsbn.S", "vd,vs,vt", MIPS_VFPU0(0x02), MA_PSP, MO_VFPU }, 607 { "vdiv.S", "vd,vs,vt", MIPS_VFPU0(0x07), MA_PSP, MO_VFPU }, 608 609 // 31-------26-----23----------------------------------------------0 610 // |= VFPU1| f | | 611 // -----6-------3--------------------------------------------------- 612 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| 613 // | VMUL | VDOT | VSCL | --- | VHDP | VDET | VCRS | --- | 614 // |-------|-------|-------|-------|-------|-------|-------|-------| 615 { "vmul.S", "vd,vs,vt", MIPS_VFPU1(0), MA_PSP, MO_VFPU }, 616 { "vdot.S", "vd,vs,vt", MIPS_VFPU1(1), MA_PSP, MO_VFPU }, 617 { "vscl.S", "vd,vs,vt", MIPS_VFPU1(2), MA_PSP, MO_VFPU }, 618 { "vhdp.S", "vd,vs,vt", MIPS_VFPU1(4), MA_PSP, MO_VFPU }, 619 { "vdet.S", "vd,vs,vt", MIPS_VFPU1(5), MA_PSP, MO_VFPU }, 620 { "vcrs.S", "vd,vs,vt", MIPS_VFPU1(6), MA_PSP, MO_VFPU }, 621 622 // 31-------26-----23----------------------------------------------0 623 // |= VFPU3| f | | 624 // -----6-------3--------------------------------------------------- 625 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| 626 // | VCMP | --- | VMIN | VMAX | --- | VSCMP | VSGE | VSLT | 627 // |-------|-------|-------|-------|-------|-------|-------|-------| 628 // VVVVVV VVV TTTTTTT z SSSSSSS z --- CCCC 629 { "vcmp.S", "C,vs,vt", MIPS_VFPU3(0), MA_PSP, MO_VFPU }, 630 { "vmin.S", "vd,vs,vt", MIPS_VFPU3(2), MA_PSP, MO_VFPU }, 631 { "vmax.S", "vd,vs,vt", MIPS_VFPU3(3), MA_PSP, MO_VFPU }, 632 { "vscmp.S", "vd,vs,vt", MIPS_VFPU3(5), MA_PSP, MO_VFPU }, 633 { "vsge.S", "vd,vs,vt", MIPS_VFPU3(6), MA_PSP, MO_VFPU }, 634 { "vslt.S", "vd,vs,vt", MIPS_VFPU3(7), MA_PSP, MO_VFPU }, 635 636 // 31-------26--------------------------------------------5--------0 637 // |=SPECIAL3| | function| 638 // -----11----------------------------------------------------6----- 639 // -----6-------5--------------------------------------------------- 640 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 641 // 000 | EXT | --- | --- | --- | INS | --- | --- | --- | 642 // 001 | --- | --- | --- | --- | --- | --- | --- | --- | 643 // 010 | --- | --- | --- | --- | --- | --- | --- | --- | 644 // 011 | --- | --- | --- | --- | --- | --- | --- | --- | 645 // 100 |ALLEGRE| --- | --- | --- | --- | --- | --- | --- | 646 // 101 | --- | --- | --- | --- | --- | --- | --- | --- | 647 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 648 // 110 | --- | --- | --- | --- | --- | --- | --- | --- | 649 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 650 { "ext", "t,s,i5,je", MIPS_SPECIAL3(0), MA_PSP }, 651 { "ins", "t,s,i5,ji", MIPS_SPECIAL3(4), MA_PSP }, 652 653 // 31-------26----------------------------------10--------5--------0 654 // |=SPECIAL3| | secfunc |ALLEGREX0| 655 // ------11---------5-------------------------------5---------6----- 656 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 657 // 00 | --- | --- | WSBH | WSBW | --- | --- | --- | --- | 658 // 01 | --- | --- | --- | --- | --- | --- | --- | --- | 659 // 10 | SEB | --- | --- | --- |BITREV | --- | --- | --- | 660 // 11 | SEH | --- | --- | --- | --- | --- | --- | --- | 661 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 662 // VVVVVV ----- ttttt ddddd VVVVV VVVVVV 663 { "wsbh", "d,t", MIPS_ALLEGREX0(0x02), MA_PSP }, 664 { "wsbh", "d", MIPS_ALLEGREX0(0x02), MA_PSP }, 665 { "wsbw", "d,t", MIPS_ALLEGREX0(0x03), MA_PSP }, 666 { "wsbw", "d", MIPS_ALLEGREX0(0x03), MA_PSP }, 667 { "seb", "d,t", MIPS_ALLEGREX0(0x10), MA_PSP }, 668 { "seb", "d", MIPS_ALLEGREX0(0x10), MA_PSP }, 669 { "bitrev", "d,t", MIPS_ALLEGREX0(0x14), MA_PSP }, 670 { "bitrev", "d", MIPS_ALLEGREX0(0x14), MA_PSP }, 671 { "seh", "d,t", MIPS_ALLEGREX0(0x18), MA_PSP }, 672 { "seh", "d", MIPS_ALLEGREX0(0x18), MA_PSP }, 673 674 675 // VFPU4: This one is a bit messy. 676 // 31-------26------21---------------------------------------------0 677 // |= VFPU4| rs | | 678 // -----6-------5--------------------------------------------------- 679 // hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 680 // 00 |VF4-1.1|VF4-1.2|VF4-1.3| VCST | --- | --- | --- | --- | 681 // 01 | --- | --- | --- | --- | --- | --- | --- | --- | 682 // 10 | VF2IN | VF2IZ | VF2IU | VF2ID | VI2F | VCMOV | --- | --- | 683 // 11 | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN | VWBN | 684 // |-------|-------|-------|-------|-------|-------|-------|-------| 685 // VVVVVV VVVVV iiiii z ------- z DDDDDDD 686 // Technically these also have names (as the second arg.) 687 { "vcst.S", "vd,Wc", MIPS_VFPU4(0x03), MA_PSP, MO_VFPU }, 688 { "vf2in.S", "vd,vs,i5", MIPS_VFPU4(0x10), MA_PSP, MO_VFPU }, 689 { "vf2iz.S", "vd,vs,i5", MIPS_VFPU4(0x11), MA_PSP, MO_VFPU }, 690 { "vf2iu.S", "vd,vs,i5", MIPS_VFPU4(0x12), MA_PSP, MO_VFPU }, 691 { "vf2id.S", "vd,vs,i5", MIPS_VFPU4(0x13), MA_PSP, MO_VFPU }, 692 { "vi2f.S", "vd,vs,i5", MIPS_VFPU4(0x14), MA_PSP, MO_VFPU }, 693 { "vcmovt.S", "vd,vs,i5", MIPS_VFPU4(0x15)|0, MA_PSP, MO_VFPU }, 694 { "vcmovf.S", "vd,vs,i5", MIPS_VFPU4(0x15)|(1<<19), MA_PSP, MO_VFPU }, 695 { "vwbn.S", "vd,vs,i5", MIPS_VFPU4(0x18), MA_PSP, MO_VFPU }, 696 697 // 31-------------21-------16--------------------------------------0 698 // |= VF4-1.1 | rt | | 699 // --------11----------5-------------------------------------------- 700 // hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 701 // 00 | VMOV | VABS | VNEG | VIDT | vsAT0 | vsAT1 | VZERO | VONE | 702 // 01 | --- | --- | --- | --- | --- | --- | --- | --- | 703 // 10 | VRCP | VRSQ | vsIN | VCOS | VEXP2 | VLOG2 | vsQRT | VASIN | 704 // 11 | VNRCP | --- | VNSIN | --- |VREXP2 | --- | --- | --- | 705 // |-------|-------|-------|-------|-------|-------|-------|-------| 706 { "vmov.S", "vd,vs", MIPS_VFPU4_11(0x00), MA_PSP, MO_VFPU }, 707 { "vabs.S", "vd,vs", MIPS_VFPU4_11(0x01), MA_PSP, MO_VFPU }, 708 { "vneg.S", "vd,vs", MIPS_VFPU4_11(0x02), MA_PSP, MO_VFPU }, 709 { "vidt.S", "vd", MIPS_VFPU4_11(0x03), MA_PSP, MO_VFPU }, 710 { "vsat0.S", "vd,vs", MIPS_VFPU4_11(0x04), MA_PSP, MO_VFPU }, 711 { "vsat1.S", "vd,vs", MIPS_VFPU4_11(0x05), MA_PSP, MO_VFPU }, 712 { "vzero.S", "vd", MIPS_VFPU4_11(0x06), MA_PSP, MO_VFPU }, 713 { "vone.S", "vd", MIPS_VFPU4_11(0x07), MA_PSP, MO_VFPU }, 714 { "vrcp.S", "vd,vs", MIPS_VFPU4_11(0x10), MA_PSP, MO_VFPU }, 715 { "vrsq.S", "vd,vs", MIPS_VFPU4_11(0x11), MA_PSP, MO_VFPU }, 716 { "vsin.S", "vd,vs", MIPS_VFPU4_11(0x12), MA_PSP, MO_VFPU }, 717 { "vcos.S", "vd,vs", MIPS_VFPU4_11(0x13), MA_PSP, MO_VFPU }, 718 { "vexp2.S", "vd,vs", MIPS_VFPU4_11(0x14), MA_PSP, MO_VFPU }, 719 { "vlog2.S", "vd,vs", MIPS_VFPU4_11(0x15), MA_PSP, MO_VFPU }, 720 { "vsqrt.S", "vd,vs", MIPS_VFPU4_11(0x16), MA_PSP, MO_VFPU }, 721 { "vasin.S", "vd,vs", MIPS_VFPU4_11(0x17), MA_PSP, MO_VFPU }, 722 { "vnrcp.S", "vd,vs", MIPS_VFPU4_11(0x18), MA_PSP, MO_VFPU }, 723 { "vnsin.S", "vd,vs", MIPS_VFPU4_11(0x1a), MA_PSP, MO_VFPU }, 724 { "vrexp2.S", "vd,vs", MIPS_VFPU4_11(0x1c), MA_PSP, MO_VFPU }, 725 726 // VFPU4 1.2: TODO: Unsure where vsBZ goes, no one uses it. 727 // 31-------------21-------16--------------------------------------0 728 // |= VF4-1.2 | rt | | 729 // --------11----------5-------------------------------------------- 730 // hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 731 // 00 | VRNDS | VRNDI |VRNDF1 |VRNDF2 | --- | --- | --- | --- | 732 // 01 | --- | --- | --- | --- | vsBZ? | --- | --- | --- | 733 // 10 | --- | --- | VF2H | VH2F | --- | --- | vsBZ? | VLGB | 734 // 11 | VUC2I | VC2I | VUS2I | vs2I | VI2UC | VI2C | VI2US | VI2S | 735 // |-------|-------|-------|-------|-------|-------|-------|-------| 736 { "vrnds.S", "vd", MIPS_VFPU4_12(0x00), MA_PSP, MO_VFPU }, 737 { "vrndi.S", "vd", MIPS_VFPU4_12(0x01), MA_PSP, MO_VFPU }, 738 { "vrndf1.S", "vd", MIPS_VFPU4_12(0x02), MA_PSP, MO_VFPU }, 739 { "vrndf2.S", "vd", MIPS_VFPU4_12(0x03), MA_PSP, MO_VFPU }, 740 // TODO: vsBZ? 741 { "vf2h.S", "vd,vs", MIPS_VFPU4_12(0x12), MA_PSP, MO_VFPU }, 742 { "vh2f.S", "vd,vs", MIPS_VFPU4_12(0x13), MA_PSP, MO_VFPU }, 743 // TODO: vsBZ? 744 { "vlgb.S", "vd,vs", MIPS_VFPU4_12(0x17), MA_PSP, MO_VFPU }, 745 { "vuc2i.S", "vd,vs", MIPS_VFPU4_12(0x18), MA_PSP, MO_VFPU }, 746 { "vc2i.S", "vd,vs", MIPS_VFPU4_12(0x19), MA_PSP, MO_VFPU }, 747 { "vus2i.S", "vd,vs", MIPS_VFPU4_12(0x1a), MA_PSP, MO_VFPU }, 748 { "vs2i.S", "vd,vs", MIPS_VFPU4_12(0x1b), MA_PSP, MO_VFPU }, 749 { "vi2uc.S", "vd,vs", MIPS_VFPU4_12(0x1c), MA_PSP, MO_VFPU }, 750 { "vi2c.S", "vd,vs", MIPS_VFPU4_12(0x1d), MA_PSP, MO_VFPU }, 751 { "vi2us.S", "vd,vs", MIPS_VFPU4_12(0x1e), MA_PSP, MO_VFPU }, 752 { "vi2s.S", "vd,vs", MIPS_VFPU4_12(0x1f), MA_PSP, MO_VFPU }, 753 754 // 31--------------21------16--------------------------------------0 755 // |= VF4-1.3 | rt | | 756 // --------11----------5-------------------------------------------- 757 // hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 758 // 00 | vsRT1 | vsRT2 | VBFY1 | VBFY2 | VOCP | vsOCP | VFAD | VAVG | 759 // 01 | vsRT3 | vsRT4 | vsGN | --- | --- | --- | --- | --- | 760 // 10 | VMFVC | VMTVC | --- | --- | --- | --- | --- | --- | 761 // 11 | --- |VT4444 |VT5551 |VT5650 | --- | --- | --- | --- | 762 // |-------|-------|-------|-------|-------|-------|-------|-------| 763 { "vsrt1.S", "vd,vs", MIPS_VFPU4_13(0x00), MA_PSP, MO_VFPU }, 764 { "vsrt2.S", "vd,vs", MIPS_VFPU4_13(0x01), MA_PSP, MO_VFPU }, 765 { "vbfy1.S", "vd,vs", MIPS_VFPU4_13(0x02), MA_PSP, MO_VFPU }, 766 { "vbfy2.S", "vd,vs", MIPS_VFPU4_13(0x03), MA_PSP, MO_VFPU }, 767 { "vocp.S", "vd,vs", MIPS_VFPU4_13(0x04), MA_PSP, MO_VFPU }, 768 { "vsocp.S", "vd,vs", MIPS_VFPU4_13(0x05), MA_PSP, MO_VFPU }, 769 { "vfad.S", "vd,vs", MIPS_VFPU4_13(0x06), MA_PSP, MO_VFPU }, 770 { "vavg.S", "vd,vs", MIPS_VFPU4_13(0x07), MA_PSP, MO_VFPU }, 771 { "vsrt3.S", "vd,vs", MIPS_VFPU4_13(0x08), MA_PSP, MO_VFPU }, 772 { "vsrt4.S", "vd,vs", MIPS_VFPU4_13(0x09), MA_PSP, MO_VFPU }, 773 { "vsgn.S", "vd,vs", MIPS_VFPU4_13(0x0a), MA_PSP, MO_VFPU }, 774 { "vmfv.S", "vs,i7", MIPS_VFPU4_13(0x10)|0x00, MA_PSP, MO_VFPU }, 775 { "vmtv.S", "vs,i7", MIPS_VFPU4_13(0x11)|0x00, MA_PSP, MO_VFPU }, 776 { "vmfvc.S", "vs,i7", MIPS_VFPU4_13(0x10)|0x80, MA_PSP, MO_VFPU }, 777 { "vmtvc.S", "vs,i7", MIPS_VFPU4_13(0x11)|0x80, MA_PSP, MO_VFPU }, 778 { "vt4444.S", "vd,vs", MIPS_VFPU4_13(0x19), MA_PSP, MO_VFPU }, 779 { "vt5551.S", "vd,vs", MIPS_VFPU4_13(0x1a), MA_PSP, MO_VFPU }, 780 { "vt5650.S", "vd,vs", MIPS_VFPU4_13(0x1b), MA_PSP, MO_VFPU }, 781 782 // 31-------26-----23----------------------------------------------0 783 // |= VFPU5| f | | 784 // -----6-------3--------------------------------------------------- 785 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 786 // | VPFXS | VPFXS | VPFXT | VPFXT | VPFXD | VPFXD | VIIM | VFIM | 787 // |-------|-------|-------|-------|-------|-------|-------|-------| 788 { "vpfxs", "Ws", MIPS_VFPU5(0), MA_PSP }, 789 { "vpfxt", "Ws", MIPS_VFPU5(2), MA_PSP }, 790 { "vpfxd", "Wd", MIPS_VFPU5(4), MA_PSP }, 791 { "viim.s", "vt,i16", MIPS_VFPU5(6), MA_PSP, MO_VFPU_SINGLE }, 792 { "vfim.s", "vt,ih", MIPS_VFPU5(7), MA_PSP, MO_VFPU_SINGLE }, 793 794 // 31-------26-----23----------------------------------------------0 795 // |= VFPU6| f | | 796 // -----6-------3--------------------------------------------------- 797 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 798 // | VMMUL | V(H)TFM2/3/4 | VMSCL | *1 | --- |VF6-1.1| 799 // |-------|-------|-------|-------|-------|-------|-------|-------| 800 // *1: vcrsp.t/vqmul.q 801 { "vmmul.S", "md,ms,mt", MIPS_VFPU6(0), MA_PSP, MO_VFPU|MO_TRANSPOSE_VS }, 802 { "vtfm2.p", "vd,ms,vt", MIPS_VFPU6(1)|MIPS_VFPUSIZE(1), MA_PSP, MO_VFPU|MO_VFPU_PAIR }, 803 { "vhtfm2.p", "vd,ms,vt", MIPS_VFPU6(2)|MIPS_VFPUSIZE(1), MA_PSP, MO_VFPU|MO_VFPU_PAIR }, 804 { "vtfm3.t", "vd,ms,vt", MIPS_VFPU6(2)|MIPS_VFPUSIZE(2), MA_PSP, MO_VFPU|MO_VFPU_TRIPLE }, 805 { "vhtfm3.t", "vd,ms,vt", MIPS_VFPU6(3)|MIPS_VFPUSIZE(2), MA_PSP, MO_VFPU|MO_VFPU_TRIPLE }, 806 { "vtfm4.q", "vd,ms,vt", MIPS_VFPU6(3)|MIPS_VFPUSIZE(3), MA_PSP, MO_VFPU|MO_VFPU_QUAD }, 807 { "vmscl.S", "md,ms,vSt", MIPS_VFPU6(4), MA_PSP, MO_VFPU }, 808 { "vcrsp.t", "vd,vs,vt", MIPS_VFPU6(5)|MIPS_VFPUSIZE(2), MA_PSP, MO_VFPU|MO_VFPU_TRIPLE }, 809 { "vqmul.q", "vd,vs,vt", MIPS_VFPU6(5)|MIPS_VFPUSIZE(3), MA_PSP, MO_VFPU|MO_VFPU_QUAD }, 810 811 // 31--------23----20----------------------------------------------0 812 // |= VF6-1.1 | f | | 813 // -----9-------3--------------------------------------------------- 814 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 815 // |VF6-1.2| --- | VROT | --- | --- | --- | --- | 816 // |-------|-------|-------|-------|-------|-------|-------|-------| 817 // VVVVVVVVVVV iiiii z SSSSSSS z DDDDDDD 818 { "vrot.S", "vd,vSs,Wr", MIPS_VFPU6_1VROT(), MA_PSP, MO_VFPU }, 819 820 // 31--------20----16----------------------------------------------0 821 // |= VF6-1.2 | f | | 822 // -----6-------4--------------------------------------------------- 823 // hi |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 824 // 0 | VMMOV | --- | --- | VMIDT | --- | --- |VMZERO | VMONE | 825 // 1 | --- | --- | --- | --- | --- | --- | --- | --- | 826 // |-------|-------|-------|-------|-------|-------|-------|-------| 827 // VVVVVVVVVVVVVVVV z SSSSSSS z DDDDDDD 828 { "vmmov.S", "md,ms", MIPS_VFPU6_2(0), MA_PSP, MO_VFPU }, 829 // VVVVVVVVVVVVVVVV z ------- z DDDDDDD 830 { "vmidt.S", "md", MIPS_VFPU6_2(3), MA_PSP, MO_VFPU }, 831 { "vmzero.S", "md", MIPS_VFPU6_2(6), MA_PSP, MO_VFPU }, 832 { "vmone.S", "md", MIPS_VFPU6_2(7), MA_PSP, MO_VFPU }, 833 834 // 31---------26------------------------------------------5--------0 835 // |= RSP| | function| 836 // ------6----------------------------------------------------6----- 837 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 838 // 000 | VMULF | VMULU | VRNDP | VMULQ | VMUDL | VMUDM | VMUDN | VMUDH | 00..07 839 // 001 | VMACF | VMACU | VRNDN | VMACQ | VMADL | VMADH | VMADN | VMADH | 08..0F 840 // 010 | VADD | VSUB | VSUT | VABS | VADDC | VSUBC | VADDB | VSUBB | 10..17 841 // 011 | VACCB | VSUCB | VSAD | VSAC | VSUM | VSAR | VACC | VSUC | 18..1F 842 // 100 | VLT | VEQ | VNE | VGE | VCL | VCH | VCR | VMRG | 20..27 843 // 101 | VAND | VNAND | VOR | VNOR | VXOR | VNXOR | --- | --- | 28..2F 844 // 110 | VRCP | VRCPL | VRCPH | VMOV | VRSQ | VRSQL | VRSQH | VNOP | 30..37 845 // 111 | VEXTT | VEXTQ | VEXTN | --- | VINST | VINSQ | VINSN | VNULL | 38..3F 846 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 847 { "vmulf", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x00), MA_RSP, 0 }, 848 { "vmulf", "Rs,RtRe", MIPS_RSP_COP2(0x00), MA_RSP, MO_RSPVRSD }, 849 { "vmulu", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x01), MA_RSP, 0 }, 850 { "vmulu", "Rs,RtRe", MIPS_RSP_COP2(0x01), MA_RSP, MO_RSPVRSD }, 851 { "vrndp", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x02), MA_RSP, 0 }, 852 { "vrndp", "Rs,RtRe", MIPS_RSP_COP2(0x02), MA_RSP, MO_RSPVRSD }, 853 { "vmulq", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x03), MA_RSP, 0 }, 854 { "vmulq", "Rs,RtRe", MIPS_RSP_COP2(0x03), MA_RSP, MO_RSPVRSD }, 855 { "vmudl", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x04), MA_RSP, 0 }, 856 { "vmudl", "Rs,RtRe", MIPS_RSP_COP2(0x04), MA_RSP, MO_RSPVRSD }, 857 { "vmudm", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x05), MA_RSP, 0 }, 858 { "vmudm", "Rs,RtRe", MIPS_RSP_COP2(0x05), MA_RSP, MO_RSPVRSD }, 859 { "vmudn", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x06), MA_RSP, 0 }, 860 { "vmudn", "Rs,RtRe", MIPS_RSP_COP2(0x06), MA_RSP, MO_RSPVRSD }, 861 { "vmudh", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x07), MA_RSP, 0 }, 862 { "vmudh", "Rs,RtRe", MIPS_RSP_COP2(0x07), MA_RSP, MO_RSPVRSD }, 863 { "vmacf", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x08), MA_RSP, 0 }, 864 { "vmacf", "Rs,RtRe", MIPS_RSP_COP2(0x08), MA_RSP, MO_RSPVRSD }, 865 { "vmacu", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x09), MA_RSP, 0 }, 866 { "vmacu", "Rs,RtRe", MIPS_RSP_COP2(0x09), MA_RSP, MO_RSPVRSD }, 867 { "vrndn", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x0a), MA_RSP, 0 }, 868 { "vrndn", "Rs,RtRe", MIPS_RSP_COP2(0x0a), MA_RSP, MO_RSPVRSD }, 869 { "vmacq", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x0b), MA_RSP, 0 }, 870 { "vmacq", "Rs,RtRe", MIPS_RSP_COP2(0x0b), MA_RSP, MO_RSPVRSD }, 871 { "vmadl", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x0c), MA_RSP, 0 }, 872 { "vmadl", "Rs,RtRe", MIPS_RSP_COP2(0x0c), MA_RSP, MO_RSPVRSD }, 873 { "vmadm", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x0d), MA_RSP, 0 }, 874 { "vmadm", "Rs,RtRe", MIPS_RSP_COP2(0x0d), MA_RSP, MO_RSPVRSD }, 875 { "vmadn", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x0e), MA_RSP, 0 }, 876 { "vmadn", "Rs,RtRe", MIPS_RSP_COP2(0x0e), MA_RSP, MO_RSPVRSD }, 877 { "vmadh", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x0f), MA_RSP, 0 }, 878 { "vmadh", "Rs,RtRe", MIPS_RSP_COP2(0x0f), MA_RSP, MO_RSPVRSD }, 879 { "vadd", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x10), MA_RSP, 0 }, 880 { "vadd", "Rs,RtRe", MIPS_RSP_COP2(0x10), MA_RSP, MO_RSPVRSD }, 881 { "vsub", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x11), MA_RSP, 0 }, 882 { "vsub", "Rs,RtRe", MIPS_RSP_COP2(0x11), MA_RSP, MO_RSPVRSD }, 883 { "vsut", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x12), MA_RSP, 0 }, 884 { "vsut", "Rs,RtRe", MIPS_RSP_COP2(0x12), MA_RSP, MO_RSPVRSD }, 885 { "vabs", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x13), MA_RSP, 0 }, 886 { "vabs", "Rs,RtRe", MIPS_RSP_COP2(0x13), MA_RSP, MO_RSPVRSD }, 887 { "vaddc", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x14), MA_RSP, 0 }, 888 { "vaddc", "Rs,RtRe", MIPS_RSP_COP2(0x14), MA_RSP, MO_RSPVRSD }, 889 { "vsubc", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x15), MA_RSP, 0 }, 890 { "vsubc", "Rs,RtRe", MIPS_RSP_COP2(0x15), MA_RSP, MO_RSPVRSD }, 891 { "vaddb", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x16), MA_RSP, 0 }, 892 { "vaddb", "Rs,RtRe", MIPS_RSP_COP2(0x16), MA_RSP, MO_RSPVRSD }, 893 { "vsubb", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x17), MA_RSP, 0 }, 894 { "vsubb", "Rs,RtRe", MIPS_RSP_COP2(0x17), MA_RSP, MO_RSPVRSD }, 895 { "vaccb", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x18), MA_RSP, 0 }, 896 { "vaccb", "Rs,RtRe", MIPS_RSP_COP2(0x18), MA_RSP, MO_RSPVRSD }, 897 { "vsucb", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x19), MA_RSP, 0 }, 898 { "vsucb", "Rs,RtRe", MIPS_RSP_COP2(0x19), MA_RSP, MO_RSPVRSD }, 899 { "vsad", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x1a), MA_RSP, 0 }, 900 { "vsad", "Rs,RtRe", MIPS_RSP_COP2(0x1a), MA_RSP, MO_RSPVRSD }, 901 { "vsac", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x1b), MA_RSP, 0 }, 902 { "vsac", "Rs,RtRe", MIPS_RSP_COP2(0x1b), MA_RSP, MO_RSPVRSD }, 903 { "vsum", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x1c), MA_RSP, 0 }, 904 { "vsum", "Rs,RtRe", MIPS_RSP_COP2(0x1c), MA_RSP, MO_RSPVRSD }, 905 { "vsar", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x1d), MA_RSP, 0 }, 906 { "vsar", "Rs,RtRe", MIPS_RSP_COP2(0x1d), MA_RSP, MO_RSPVRSD }, 907 { "vacc", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x1e), MA_RSP, 0 }, 908 { "vacc", "Rs,RtRe", MIPS_RSP_COP2(0x1e), MA_RSP, MO_RSPVRSD }, 909 { "vsuc", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x1f), MA_RSP, 0 }, 910 { "vsuc", "Rs,RtRe", MIPS_RSP_COP2(0x1f), MA_RSP, MO_RSPVRSD }, 911 { "vlt", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x20), MA_RSP, 0 }, 912 { "vlt", "Rs,RtRe", MIPS_RSP_COP2(0x20), MA_RSP, MO_RSPVRSD }, 913 { "veq", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x21), MA_RSP, 0 }, 914 { "veq", "Rs,RtRe", MIPS_RSP_COP2(0x21), MA_RSP, MO_RSPVRSD }, 915 { "vne", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x22), MA_RSP, 0 }, 916 { "vne", "Rs,RtRe", MIPS_RSP_COP2(0x22), MA_RSP, MO_RSPVRSD }, 917 { "vge", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x23), MA_RSP, 0 }, 918 { "vge", "Rs,RtRe", MIPS_RSP_COP2(0x23), MA_RSP, MO_RSPVRSD }, 919 { "vcl", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x24), MA_RSP, 0 }, 920 { "vcl", "Rs,RtRe", MIPS_RSP_COP2(0x24), MA_RSP, MO_RSPVRSD }, 921 { "vch", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x25), MA_RSP, 0 }, 922 { "vch", "Rs,RtRe", MIPS_RSP_COP2(0x25), MA_RSP, MO_RSPVRSD }, 923 { "vcr", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x26), MA_RSP, 0 }, 924 { "vcr", "Rs,RtRe", MIPS_RSP_COP2(0x26), MA_RSP, MO_RSPVRSD }, 925 { "vmrg", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x27), MA_RSP, 0 }, 926 { "vmrg", "Rs,RtRe", MIPS_RSP_COP2(0x27), MA_RSP, MO_RSPVRSD }, 927 { "vand", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x28), MA_RSP, 0 }, 928 { "vand", "Rs,RtRe", MIPS_RSP_COP2(0x28), MA_RSP, MO_RSPVRSD }, 929 { "vnand", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x29), MA_RSP, 0 }, 930 { "vnand", "Rs,RtRe", MIPS_RSP_COP2(0x29), MA_RSP, MO_RSPVRSD }, 931 { "vor", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x2a), MA_RSP, 0 }, 932 { "vor", "Rs,RtRe", MIPS_RSP_COP2(0x2a), MA_RSP, MO_RSPVRSD }, 933 { "vnor", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x2b), MA_RSP, 0 }, 934 { "vnor", "Rs,RtRe", MIPS_RSP_COP2(0x2b), MA_RSP, MO_RSPVRSD }, 935 { "vxor", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x2c), MA_RSP, 0 }, 936 { "vxor", "Rs,RtRe", MIPS_RSP_COP2(0x2c), MA_RSP, MO_RSPVRSD }, 937 { "vnxor", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x2d), MA_RSP, 0 }, 938 { "vnxor", "Rs,RtRe", MIPS_RSP_COP2(0x2d), MA_RSP, MO_RSPVRSD }, 939 { "vrcp", "RdRm,RtRl", MIPS_RSP_COP2(0x30), MA_RSP, 0 }, 940 { "vrcpl", "RdRm,RtRl", MIPS_RSP_COP2(0x31), MA_RSP, 0 }, 941 { "vrcph", "RdRm,RtRl", MIPS_RSP_COP2(0x32), MA_RSP, 0 }, 942 { "vmov", "RdRm,RtRl", MIPS_RSP_COP2(0x33), MA_RSP, 0 }, 943 { "vrsq", "RdRm,RtRl", MIPS_RSP_COP2(0x34), MA_RSP, 0 }, 944 { "vrsql", "RdRm,RtRl", MIPS_RSP_COP2(0x35), MA_RSP, 0 }, 945 { "vrsqh", "RdRm,RtRl", MIPS_RSP_COP2(0x36), MA_RSP, 0 }, 946 { "vnop", "", MIPS_RSP_COP2(0x37), MA_RSP, 0 }, 947 { "vextt", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x38), MA_RSP, 0 }, 948 { "vextt", "Rs,RtRe", MIPS_RSP_COP2(0x38), MA_RSP, MO_RSPVRSD }, 949 { "vextq", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x39), MA_RSP, 0 }, 950 { "vextq", "Rs,RtRe", MIPS_RSP_COP2(0x39), MA_RSP, MO_RSPVRSD }, 951 { "vextn", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x3a), MA_RSP, 0 }, 952 { "vextn", "Rs,RtRe", MIPS_RSP_COP2(0x3a), MA_RSP, MO_RSPVRSD }, 953 { "vinst", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x3c), MA_RSP, 0 }, 954 { "vinst", "Rs,RtRe", MIPS_RSP_COP2(0x3c), MA_RSP, MO_RSPVRSD }, 955 { "vinsq", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x3d), MA_RSP, 0 }, 956 { "vinsq", "Rs,RtRe", MIPS_RSP_COP2(0x3d), MA_RSP, MO_RSPVRSD }, 957 { "vinsn", "Rd,Rs,RtRe", MIPS_RSP_COP2(0x3e), MA_RSP, 0 }, 958 { "vinsn", "Rs,RtRe", MIPS_RSP_COP2(0x3e), MA_RSP, MO_RSPVRSD }, 959 { "vnull", "", MIPS_RSP_COP2(0x3f), MA_RSP, 0 }, 960 961 // 31---------26--------------------15-------11--------------------0 962 // |= LWC2| | rd | | 963 // -----6----------------------5------------------------------------ 964 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 965 // 00 | LBV | LSV | LLV | LDV | LQV | LRV | LPV | LUV | 00..07 966 // 01 | LHV | LFV | LWV | LTV | --- | --- | --- | --- | 08..0F 967 // 10 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17 968 // 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 969 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 970 {"lbv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x00), MA_RSP, 0 }, 971 {"lbv", "RtRo,(s)", MIPS_RSP_LWC2(0x00), MA_RSP, 0 }, 972 {"lsv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x01), MA_RSP, MO_RSP_HWOFFSET }, 973 {"lsv", "RtRo,(s)", MIPS_RSP_LWC2(0x01), MA_RSP, MO_RSP_HWOFFSET }, 974 {"llv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x02), MA_RSP, MO_RSP_WOFFSET }, 975 {"llv", "RtRo,(s)", MIPS_RSP_LWC2(0x02), MA_RSP, MO_RSP_WOFFSET }, 976 {"ldv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x03), MA_RSP, MO_RSP_DWOFFSET }, 977 {"ldv", "RtRo,(s)", MIPS_RSP_LWC2(0x03), MA_RSP, MO_RSP_DWOFFSET }, 978 {"lqv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x04), MA_RSP, MO_RSP_QWOFFSET }, 979 {"lqv", "RtRo,(s)", MIPS_RSP_LWC2(0x04), MA_RSP, MO_RSP_QWOFFSET }, 980 {"lrv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x05), MA_RSP, MO_RSP_QWOFFSET }, 981 {"lrv", "RtRo,(s)", MIPS_RSP_LWC2(0x05), MA_RSP, MO_RSP_QWOFFSET }, 982 {"lpv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x06), MA_RSP, MO_RSP_DWOFFSET }, 983 {"lpv", "RtRo,(s)", MIPS_RSP_LWC2(0x06), MA_RSP, MO_RSP_DWOFFSET }, 984 {"luv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x07), MA_RSP, MO_RSP_DWOFFSET }, 985 {"luv", "RtRo,(s)", MIPS_RSP_LWC2(0x07), MA_RSP, MO_RSP_DWOFFSET }, 986 {"lhv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x08), MA_RSP, MO_RSP_QWOFFSET }, 987 {"lhv", "RtRo,(s)", MIPS_RSP_LWC2(0x08), MA_RSP, MO_RSP_QWOFFSET }, 988 {"lfv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x09), MA_RSP, MO_RSP_QWOFFSET }, 989 {"lfv", "RtRo,(s)", MIPS_RSP_LWC2(0x09), MA_RSP, MO_RSP_QWOFFSET }, 990 {"lwv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x0a), MA_RSP, MO_RSP_QWOFFSET }, 991 {"lwv", "RtRo,(s)", MIPS_RSP_LWC2(0x0a), MA_RSP, MO_RSP_QWOFFSET }, 992 {"ltv", "RtRo,i7(s)", MIPS_RSP_LWC2(0x0b), MA_RSP, MO_RSP_QWOFFSET }, 993 {"ltv", "RtRo,(s)", MIPS_RSP_LWC2(0x0b), MA_RSP, MO_RSP_QWOFFSET }, 994 995 // 31---------26--------------------15-------11--------------------0 996 // |= SWC2| | rd | | 997 // -----6----------------------5------------------------------------ 998 // |--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo 999 // 00 | SBV | SSV | SLV | SDV | SQV | SRV | SPV | SUV | 00..07 1000 // 01 | SHV | SFV | SWV | STV | --- | --- | --- | --- | 08..0F 1001 // 10 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17 1002 // 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F 1003 // hi |-------|-------|-------|-------|-------|-------|-------|-------| 1004 {"sbv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x00), MA_RSP, 0 }, 1005 {"sbv", "RtRo,(s)", MIPS_RSP_SWC2(0x00), MA_RSP, 0 }, 1006 {"ssv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x01), MA_RSP, MO_RSP_HWOFFSET }, 1007 {"ssv", "RtRo,(s)", MIPS_RSP_SWC2(0x01), MA_RSP, MO_RSP_HWOFFSET }, 1008 {"slv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x02), MA_RSP, MO_RSP_WOFFSET }, 1009 {"slv", "RtRo,(s)", MIPS_RSP_SWC2(0x02), MA_RSP, MO_RSP_WOFFSET }, 1010 {"sdv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x03), MA_RSP, MO_RSP_DWOFFSET }, 1011 {"sdv", "RtRo,(s)", MIPS_RSP_SWC2(0x03), MA_RSP, MO_RSP_DWOFFSET }, 1012 {"sqv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x04), MA_RSP, MO_RSP_QWOFFSET }, 1013 {"sqv", "RtRo,(s)", MIPS_RSP_SWC2(0x04), MA_RSP, MO_RSP_QWOFFSET }, 1014 {"srv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x05), MA_RSP, MO_RSP_QWOFFSET }, 1015 {"srv", "RtRo,(s)", MIPS_RSP_SWC2(0x05), MA_RSP, MO_RSP_QWOFFSET }, 1016 {"spv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x06), MA_RSP, MO_RSP_DWOFFSET }, 1017 {"spv", "RtRo,(s)", MIPS_RSP_SWC2(0x06), MA_RSP, MO_RSP_DWOFFSET }, 1018 {"suv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x07), MA_RSP, MO_RSP_DWOFFSET }, 1019 {"suv", "RtRo,(s)", MIPS_RSP_SWC2(0x07), MA_RSP, MO_RSP_DWOFFSET }, 1020 {"shv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x08), MA_RSP, MO_RSP_QWOFFSET }, 1021 {"shv", "RtRo,(s)", MIPS_RSP_SWC2(0x08), MA_RSP, MO_RSP_QWOFFSET }, 1022 {"sfv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x09), MA_RSP, MO_RSP_QWOFFSET }, 1023 {"sfv", "RtRo,(s)", MIPS_RSP_SWC2(0x09), MA_RSP, MO_RSP_QWOFFSET }, 1024 {"swv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x0a), MA_RSP, MO_RSP_QWOFFSET }, 1025 {"swv", "RtRo,(s)", MIPS_RSP_SWC2(0x0a), MA_RSP, MO_RSP_QWOFFSET }, 1026 {"stv", "RtRo,i7(s)", MIPS_RSP_SWC2(0x0b), MA_RSP, MO_RSP_QWOFFSET }, 1027 {"stv", "RtRo,(s)", MIPS_RSP_SWC2(0x0b), MA_RSP, MO_RSP_QWOFFSET }, 1028 // END 1029 { nullptr, nullptr, 0, 0 } 1030 }; 1031 1032 const MipsArchDefinition mipsArchs[] = { 1033 // MARCH_PSX 1034 { "PSX", MA_MIPS1|MA_PSX, MA_EXPSX, 0 }, 1035 // MARCH_N64 1036 { "N64", MA_MIPS1|MA_MIPS2|MA_MIPS3, MA_EXN64, MO_64BIT|MO_FPU|MO_DFPU }, 1037 // MARCH_PS2 1038 { "PS2", MA_MIPS1|MA_MIPS2|MA_MIPS3|MA_PS2, MA_EXPS2, MO_64BIT|MO_FPU }, 1039 // MARCH_PSP 1040 { "PSP", MA_MIPS1|MA_MIPS2|MA_MIPS3|MA_PSP, MA_EXPSP, MO_FPU }, 1041 // MARCH_RSP 1042 { "RSP", MA_MIPS1|MA_RSP, MA_EXRSP, 0 }, 1043 // MARCH_INVALID 1044 { "Invalid", 0, 0, 0 }, 1045 }; 1046