/dports/emulators/ppsspp-qt5/ppsspp-1.12.3/ext/armips/Archs/MIPS/ |
H A D | MipsOpcodes.cpp | 28 { "addi", "t,s,i16", MIPS_OP(0x08), MA_MIPS1, MO_IGNORERTD }, 32 { "addiu", "t,s,i16", MIPS_OP(0x09), MA_MIPS1, MO_IGNORERTD }, 36 { "slti", "t,s,i16", MIPS_OP(0x0A), MA_MIPS1, MO_IGNORERTD }, 38 { "sltiu", "t,s,i16", MIPS_OP(0x0B), MA_MIPS1, MO_IGNORERTD }, 40 { "andi", "t,s,i16", MIPS_OP(0x0C), MA_MIPS1, MO_IGNORERTD }, 42 { "ori", "t,s,i16", MIPS_OP(0x0D), MA_MIPS1, MO_IGNORERTD }, 44 { "xori", "t,s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_IGNORERTD }, 46 { "lui", "t,i16", MIPS_OP(0x0F), MA_MIPS1, MO_IGNORERTD }, 67 { "lq", "t,(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 69 { "sq", "t,(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, [all …]
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H A D | MipsOpcodes.h | 27 #define MO_IGNORERTD 0x00000100 // don't care for rt delay macro
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H A D | CMipsInstruction.cpp | 224 && !(opcodeData.opcode.flags & MO_IGNORERTD)) in Validate()
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/dports/emulators/ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/ |
H A D | MipsOpcodes.cpp | 28 { "addi", "t,s,i16", MIPS_OP(0x08), MA_MIPS1, MO_IGNORERTD }, 32 { "addiu", "t,s,i16", MIPS_OP(0x09), MA_MIPS1, MO_IGNORERTD }, 36 { "slti", "t,s,i16", MIPS_OP(0x0A), MA_MIPS1, MO_IGNORERTD }, 38 { "sltiu", "t,s,i16", MIPS_OP(0x0B), MA_MIPS1, MO_IGNORERTD }, 40 { "andi", "t,s,i16", MIPS_OP(0x0C), MA_MIPS1, MO_IGNORERTD }, 42 { "ori", "t,s,i16", MIPS_OP(0x0D), MA_MIPS1, MO_IGNORERTD }, 44 { "xori", "t,s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_IGNORERTD }, 46 { "lui", "t,i16", MIPS_OP(0x0F), MA_MIPS1, MO_IGNORERTD }, 67 { "lq", "t,(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 69 { "sq", "t,(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, [all …]
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H A D | MipsOpcodes.h | 27 #define MO_IGNORERTD 0x00000100 // don't care for rt delay macro
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H A D | CMipsInstruction.cpp | 224 && !(opcodeData.opcode.flags & MO_IGNORERTD)) in Validate()
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/dports/emulators/libretro-ppsspp/ppsspp-1.12.3/ext/armips/Archs/MIPS/ |
H A D | MipsOpcodes.cpp | 28 { "addi", "t,s,i16", MIPS_OP(0x08), MA_MIPS1, MO_IGNORERTD }, 32 { "addiu", "t,s,i16", MIPS_OP(0x09), MA_MIPS1, MO_IGNORERTD }, 36 { "slti", "t,s,i16", MIPS_OP(0x0A), MA_MIPS1, MO_IGNORERTD }, 38 { "sltiu", "t,s,i16", MIPS_OP(0x0B), MA_MIPS1, MO_IGNORERTD }, 40 { "andi", "t,s,i16", MIPS_OP(0x0C), MA_MIPS1, MO_IGNORERTD }, 42 { "ori", "t,s,i16", MIPS_OP(0x0D), MA_MIPS1, MO_IGNORERTD }, 44 { "xori", "t,s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_IGNORERTD }, 46 { "lui", "t,i16", MIPS_OP(0x0F), MA_MIPS1, MO_IGNORERTD }, 67 { "lq", "t,(s)", MIPS_OP(0x1E), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, 69 { "sq", "t,(s)", MIPS_OP(0x1F), MA_PS2, MO_DELAYRT|MO_IGNORERTD }, [all …]
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H A D | MipsOpcodes.h | 27 #define MO_IGNORERTD 0x00000100 // don't care for rt delay macro
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H A D | CMipsInstruction.cpp | 224 && !(opcodeData.opcode.flags & MO_IGNORERTD)) in Validate()
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