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Searched refs:MUX_DATA0 (Results 1 – 2 of 2) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/fifo/
H A Dfifo19_mux.v44 localparam MUX_DATA0 = 1; constant
63 state <= MUX_DATA0;
67 MUX_DATA0 :
75 state <= MUX_DATA0;
85 assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
87 assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
88 assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;
H A Dfifo36_mux.v44 localparam MUX_DATA0 = 1; constant
63 state <= MUX_DATA0;
67 MUX_DATA0 :
75 state <= MUX_DATA0;
85 assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
87 assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
88 assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;