1//
2// Copyright 2011 Ettus Research LLC
3//
4// This program is free software: you can redistribute it and/or modify
5// it under the terms of the GNU General Public License as published by
6// the Free Software Foundation, either version 3 of the License, or
7// (at your option) any later version.
8//
9// This program is distributed in the hope that it will be useful,
10// but WITHOUT ANY WARRANTY; without even the implied warranty of
11// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12// GNU General Public License for more details.
13//
14// You should have received a copy of the GNU General Public License
15// along with this program.  If not, see <http://www.gnu.org/licenses/>.
16//
17
18
19// Mux packets from multiple FIFO interfaces onto a single one.
20//  Can alternate or give priority to one port (port 0)
21//  In prio mode, port 1 will never get access if port 0 is always busy
22
23module fifo36_mux
24  #(parameter prio = 0)
25   (input clk, input reset, input clear,
26    input [35:0] data0_i, input src0_rdy_i, output dst0_rdy_o,
27    input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
28    output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
29
30   wire [35:0] 	  data0_int, data1_int;
31   wire 	  src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int;
32
33   fifo_short #(.WIDTH(36)) mux_fifo_in0
34     (.clk(clk), .reset(reset), .clear(clear),
35      .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o),
36      .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int));
37
38   fifo_short #(.WIDTH(36)) mux_fifo_in1
39     (.clk(clk), .reset(reset), .clear(clear),
40      .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o),
41      .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int));
42
43   localparam MUX_IDLE0 = 0;
44   localparam MUX_DATA0 = 1;
45   localparam MUX_IDLE1 = 2;
46   localparam MUX_DATA1 = 3;
47
48   reg [1:0] 	  state;
49
50   wire 	  eof0 = data0_int[33];
51   wire 	  eof1 = data1_int[33];
52
53   wire [35:0] 	  data_int;
54   wire 	  src_rdy_int, dst_rdy_int;
55
56   always @(posedge clk)
57     if(reset | clear)
58       state <= MUX_IDLE0;
59     else
60       case(state)
61	 MUX_IDLE0 :
62	   if(src0_rdy_int)
63	     state <= MUX_DATA0;
64	   else if(src1_rdy_int)
65	     state <= MUX_DATA1;
66
67	 MUX_DATA0 :
68	   if(src0_rdy_int & dst_rdy_int & eof0)
69	     state <= prio ? MUX_IDLE0 : MUX_IDLE1;
70
71	 MUX_IDLE1 :
72	   if(src1_rdy_int)
73	     state <= MUX_DATA1;
74	   else if(src0_rdy_int)
75	     state <= MUX_DATA0;
76
77	 MUX_DATA1 :
78	   if(src1_rdy_int & dst_rdy_int & eof1)
79	     state <= MUX_IDLE0;
80
81	 default :
82	   state <= MUX_IDLE0;
83       endcase // case (state)
84
85   assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
86   assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0;
87   assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
88   assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;
89
90   fifo_short #(.WIDTH(36)) mux_fifo
91     (.clk(clk), .reset(reset), .clear(clear),
92      .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
93      .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
94endmodule // fifo36_demux
95