/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 172 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 180 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 192 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 214 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 295 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 434 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 590 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 644 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 782 OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3); in update_vsc_pipe() [all …]
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/freedreno/a3xx/ |
H A D | fd3_gmem.c | 192 OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2); in emit_binning_workaround() 200 OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4); in emit_binning_workaround() 213 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1); in emit_binning_workaround() 235 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1); in emit_binning_workaround() 256 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in emit_binning_workaround() 317 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in emit_binning_workaround() 460 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_gmem2mem() 620 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2); in fd3_emit_tile_mem2gmem() 675 OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4); in fd3_emit_tile_mem2gmem() 964 OUT_PKT0(ring, REG_A3XX_VSC_BIN_SIZE, 1); in fd3_emit_tile_init() [all …]
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 170 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 199 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 243 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 249 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 287 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 528 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 612 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 659 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() 706 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3); in fd4_emit_tile_prep() 722 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3); in fd4_emit_tile_prep() [all …]
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/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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H A D | fd4_emit.c | 256 OUT_PKT0(ring, bcolor_reg[sb], 1); in emit_textures() 795 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1); in fd4_emit_restore() 798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1); in fd4_emit_restore() 814 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1); in fd4_emit_restore() 817 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1); in fd4_emit_restore() 820 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1); in fd4_emit_restore() 823 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1); in fd4_emit_restore() 829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1); in fd4_emit_restore() 832 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4); in fd4_emit_restore() 860 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1); in fd4_emit_restore() [all …]
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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H A D | fd4_emit.c | 256 OUT_PKT0(ring, bcolor_reg[sb], 1); in emit_textures() 795 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1); in fd4_emit_restore() 798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1); in fd4_emit_restore() 814 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1); in fd4_emit_restore() 817 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1); in fd4_emit_restore() 820 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1); in fd4_emit_restore() 823 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1); in fd4_emit_restore() 829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1); in fd4_emit_restore() 832 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4); in fd4_emit_restore() 860 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1); in fd4_emit_restore() [all …]
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/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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H A D | fd4_emit.c | 256 OUT_PKT0(ring, bcolor_reg[sb], 1); in emit_textures() 795 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1); in fd4_emit_restore() 798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1); in fd4_emit_restore() 814 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1); in fd4_emit_restore() 817 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1); in fd4_emit_restore() 820 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1); in fd4_emit_restore() 823 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1); in fd4_emit_restore() 829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1); in fd4_emit_restore() 832 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4); in fd4_emit_restore() 860 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1); in fd4_emit_restore() [all …]
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/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_gmem.c | 184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4); in emit_gmem2mem_surf() 214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1); in fd4_emit_tile_gmem2mem() 255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1); in fd4_emit_tile_gmem2mem() 299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_gmem2mem() 430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1); in fd4_emit_tile_mem2gmem() 445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1); in fd4_emit_tile_mem2gmem() 546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in fd4_emit_sysmem_prep() 630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1); in emit_binning_pass() 676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1); in fd4_emit_tile_init() [all …]
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