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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
H A DX86InstrControl.td36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
136 OpSize32, Sched<[WriteJump]>;
139 OpSize32, Sched<[WriteJumpLd]>;
172 OpSize32, Sched<[WriteJump]>, NOTRACK;
194 OpSize32, Sched<[WriteJump]>;
226 "call{l}\t$dst", []>, OpSize32,
246 OpSize32,
[all …]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
H A DX86InstrControl.td36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
136 OpSize32, Sched<[WriteJump]>;
139 OpSize32, Sched<[WriteJumpLd]>;
172 OpSize32, Sched<[WriteJump]>, NOTRACK;
194 OpSize32, Sched<[WriteJump]>;
226 "call{l}\t$dst", []>, OpSize32,
246 OpSize32,
[all …]
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
H A DX86InstrControl.td36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
136 OpSize32, Sched<[WriteJump]>;
139 OpSize32, Sched<[WriteJumpLd]>;
172 OpSize32, Sched<[WriteJump]>, NOTRACK;
194 OpSize32, Sched<[WriteJump]>;
226 "call{l}\t$dst", []>, OpSize32,
246 OpSize32,
[all …]
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
H A DX86InstrControl.td36 "{l}ret{l|f}", []>, OpSize32;
42 "{l}ret{l|f}\t$amt", []>, OpSize32;
68 "jmp\t$dst", []>, OpSize32;
87 []>, TB, OpSize32;
136 OpSize32, Sched<[WriteJump]>;
139 OpSize32, Sched<[WriteJumpLd]>;
172 OpSize32, Sched<[WriteJump]>, NOTRACK;
194 OpSize32, Sched<[WriteJump]>;
224 "call{l}\t$dst", []>, OpSize32,
244 OpSize32,
[all …]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
58 OpSize32, Sched<[WriteALU]>;
62 OpSize32, TB, Sched<[WriteALULd]>;
76 OpSize32, Sched<[WriteALU]>;
80 OpSize32, Sched<[WriteALULd]>;
84 OpSize32, Sched<[WriteALU]>;
88 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/X86/
H A DX86InstrExtension.td19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
26 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
51 OpSize32, Sched<[WriteALU]>;
55 OpSize32, Sched<[WriteALULd]>;
59 OpSize32, Sched<[WriteALU]>;
63 OpSize32, TB, Sched<[WriteALULd]>;
77 OpSize32, Sched<[WriteALU]>;
81 OpSize32, Sched<[WriteALULd]>;
85 OpSize32, Sched<[WriteALU]>;
89 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/X86/
H A DX86InstrExtension.td20 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
27 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
52 OpSize32, Sched<[WriteALU]>;
56 OpSize32, Sched<[WriteALULd]>;
60 OpSize32, Sched<[WriteALU]>;
64 OpSize32, TB, Sched<[WriteALULd]>;
78 OpSize32, Sched<[WriteALU]>;
82 OpSize32, Sched<[WriteALULd]>;
86 OpSize32, Sched<[WriteALU]>;
90 TB, OpSize32, Sched<[WriteALULd]>;
[all …]
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/X86/
H A DX86InstrControl.td37 "{l}ret{l|f}", []>, OpSize32;
43 "{l}ret{l|f}\t$amt", []>, OpSize32;
69 "jmp\t$dst", []>, OpSize32;
82 []>, TB, OpSize32;
132 OpSize32, Sched<[WriteJump]>;
135 OpSize32, Sched<[WriteJumpLd]>;
157 OpSize32, Sched<[WriteJump]>, NOTRACK;
179 OpSize32, Sched<[WriteJump]>;
209 "call{l}\t$dst", []>, OpSize32,
228 OpSize32,
[all …]
/dports/emulators/qemu/qemu-6.2.0/capstone/suite/synctools/tablegen/X86/back/
H A DX86InstrControl.td37 "{l}ret{l|f}", []>, OpSize32;
43 "{l}ret{l|f}\t$amt", []>, OpSize32;
69 "jmp\t$dst", []>, OpSize32;
82 []>, TB, OpSize32;
132 OpSize32, Sched<[WriteJump]>;
135 OpSize32, Sched<[WriteJumpLd]>;
157 OpSize32, Sched<[WriteJump]>, NOTRACK;
179 OpSize32, Sched<[WriteJump]>;
209 "call{l}\t$dst", []>, OpSize32,
228 OpSize32,
[all …]
/dports/emulators/qemu5/qemu-5.2.0/capstone/suite/synctools/tablegen/X86/back/
H A DX86InstrControl.td37 "{l}ret{l|f}", []>, OpSize32;
43 "{l}ret{l|f}\t$amt", []>, OpSize32;
69 "jmp\t$dst", []>, OpSize32;
82 []>, TB, OpSize32;
132 OpSize32, Sched<[WriteJump]>;
135 OpSize32, Sched<[WriteJumpLd]>;
157 OpSize32, Sched<[WriteJump]>, NOTRACK;
179 OpSize32, Sched<[WriteJump]>;
209 "call{l}\t$dst", []>, OpSize32,
228 OpSize32,
[all …]
/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/X86/
H A DX86InstrControl.td37 "{l}ret{l|f}", []>, OpSize32;
43 "{l}ret{l|f}\t$amt", []>, OpSize32;
69 "jmp\t$dst", []>, OpSize32;
82 []>, TB, OpSize32;
132 OpSize32, Sched<[WriteJump]>;
135 OpSize32, Sched<[WriteJumpLd]>;
157 OpSize32, Sched<[WriteJump]>, NOTRACK;
179 OpSize32, Sched<[WriteJump]>;
209 "call{l}\t$dst", []>, OpSize32,
228 OpSize32,
[all …]
/dports/emulators/qemu60/qemu-6.0.0/capstone/suite/synctools/tablegen/X86/back/
H A DX86InstrControl.td37 "{l}ret{l|f}", []>, OpSize32;
43 "{l}ret{l|f}\t$amt", []>, OpSize32;
69 "jmp\t$dst", []>, OpSize32;
82 []>, TB, OpSize32;
132 OpSize32, Sched<[WriteJump]>;
135 OpSize32, Sched<[WriteJumpLd]>;
157 OpSize32, Sched<[WriteJump]>, NOTRACK;
179 OpSize32, Sched<[WriteJump]>;
209 "call{l}\t$dst", []>, OpSize32,
228 OpSize32,
[all …]

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