1//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the X86 jump, return, call, and related instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Control Flow Instructions. 16// 17 18// Return instructions. 19// 20// The X86retflag return instructions are variadic because we may add ST0 and 21// ST1 arguments when returning values on the x87 stack. 22let isTerminator = 1, isReturn = 1, isBarrier = 1, 23 hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { 24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), 25 "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>; 26 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), 27 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>; 28 def RETW : I <0xC3, RawFrm, (outs), (ins), 29 "ret{w}", []>, OpSize16; 30 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 31 "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>; 32 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), 33 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>; 34 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), 35 "ret{w}\t$amt", []>, OpSize16; 36 def LRETL : I <0xCB, RawFrm, (outs), (ins), 37 "{l}ret{l|f}", []>, OpSize32; 38 def LRETQ : RI <0xCB, RawFrm, (outs), (ins), 39 "{l}ret{|f}q", []>, Requires<[In64BitMode]>; 40 def LRETW : I <0xCB, RawFrm, (outs), (ins), 41 "{l}ret{w|f}", []>, OpSize16; 42 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 43 "{l}ret{l|f}\t$amt", []>, OpSize32; 44 def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 45 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>; 46 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), 47 "{l}ret{w|f}\t$amt", []>, OpSize16; 48 49 // The machine return from interrupt instruction, but sometimes we need to 50 // perform a post-epilogue stack adjustment. Codegen emits the pseudo form 51 // which expands to include an SP adjustment if necessary. 52 def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, 53 OpSize16; 54 def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; 55 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; 56 // let isCodeGenOnly = 1 in 57 // def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; 58 // def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; 59} 60 61// Unconditional branches. 62let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { 63 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), 64 "jmp\t$dst", [(br bb:$dst)]>; 65 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 66 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), 67 "jmp\t$dst", []>, OpSize16; 68 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), 69 "jmp\t$dst", []>, OpSize32; 70 } 71} 72 73// Conditional Branches. 74let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { 75 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { 76 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, 77 [(X86brcond bb:$dst, Cond, EFLAGS)]>; 78 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { 79 def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm, 80 []>, OpSize16, TB; 81 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm, 82 []>, TB, OpSize32; 83 } 84 } 85} 86 87defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>; 88defm JNO : ICBr<0x71, 0x81, "jno\t$dst", X86_COND_NO>; 89defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>; 90defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>; 91defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>; 92defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>; 93defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>; 94defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>; 95defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>; 96defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>; 97defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>; 98defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>; 99defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>; 100defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>; 101defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>; 102defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>; 103 104// jcx/jecx/jrcx instructions. 105let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in { 106 // These are the 32-bit versions of this instruction for the asmparser. In 107 // 32-bit mode, the address size prefix is jcxz and the unprefixed version is 108 // jecxz. 109 let Uses = [CX] in 110 def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 111 "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>; 112 let Uses = [ECX] in 113 def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 114 "jecxz\t$dst", []>, AdSize32; 115 116 let Uses = [RCX] in 117 def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), 118 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>; 119} 120 121// Indirect branches 122let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 123 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", 124 [(brind GR16:$dst)]>, Requires<[Not64BitMode]>, 125 OpSize16, Sched<[WriteJump]>; 126 def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", 127 [(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>, 128 OpSize16, Sched<[WriteJumpLd]>; 129 130 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", 131 [(brind GR32:$dst)]>, Requires<[Not64BitMode]>, 132 OpSize32, Sched<[WriteJump]>; 133 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", 134 [(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>, 135 OpSize32, Sched<[WriteJumpLd]>; 136 137 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", 138 [(brind GR64:$dst)]>, Requires<[In64BitMode]>, 139 Sched<[WriteJump]>; 140 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", 141 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>, 142 Sched<[WriteJumpLd]>; 143 144 // Non-tracking jumps for IBT, use with caution. 145 let isCodeGenOnly = 1 in { 146 def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst", 147 [(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>, 148 OpSize16, Sched<[WriteJump]>, NOTRACK; 149 150 def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst", 151 [(X86NoTrackBrind (loadi16 addr : $dst))]>, 152 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>, 153 NOTRACK; 154 155 def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst", 156 [(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>, 157 OpSize32, Sched<[WriteJump]>, NOTRACK; 158 def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst", 159 [(X86NoTrackBrind (loadi32 addr : $dst))]>, 160 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>, 161 NOTRACK; 162 163 def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst", 164 [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>, 165 Sched<[WriteJump]>, NOTRACK; 166 def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst", 167 [(X86NoTrackBrind(loadi64 addr : $dst))]>, 168 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK; 169 } 170 171 let Predicates = [Not64BitMode], AsmVariantName = "att" in { 172 def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), 173 (ins i16imm:$off, i16imm:$seg), 174 "ljmp{w}\t$seg : $off", []>, 175 OpSize16, Sched<[WriteJump]>; 176 def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), 177 (ins i32imm:$off, i16imm:$seg), 178 "ljmp{l}\t$seg : $off", []>, 179 OpSize32, Sched<[WriteJump]>; 180 } 181 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 182 "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>; 183 184 let AsmVariantName = "att" in 185 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 186 "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; 187 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), 188 "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; 189} 190 191// Loop instructions 192let SchedRW = [WriteJump] in { 193def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; 194def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; 195def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; 196} 197 198//===----------------------------------------------------------------------===// 199// Call Instructions... 200// 201let isCall = 1 in 202 // All calls clobber the non-callee saved registers. ESP is marked as 203 // a use to prevent stack-pointer assignments that appear immediately 204 // before calls from potentially appearing dead. Uses for argument 205 // registers are added manually. 206 let Uses = [ESP, SSP] in { 207 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, 208 (outs), (ins i32imm_pcrel:$dst), 209 "call{l}\t$dst", []>, OpSize32, 210 Requires<[Not64BitMode]>, Sched<[WriteJump]>; 211 let hasSideEffects = 0 in 212 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, 213 (outs), (ins i16imm_pcrel:$dst), 214 "call{w}\t$dst", []>, OpSize16, 215 Sched<[WriteJump]>; 216 def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), 217 "call{w}\t{*}$dst", [(X86call GR16:$dst)]>, 218 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; 219 def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), 220 "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>, 221 OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, 222 Sched<[WriteJumpLd]>; 223 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), 224 "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32, 225 Requires<[Not64BitMode,NotUseRetpoline]>, Sched<[WriteJump]>; 226 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), 227 "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, 228 OpSize32, 229 Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>, 230 Sched<[WriteJumpLd]>; 231 232 // Non-tracking calls for IBT, use with caution. 233 let isCodeGenOnly = 1 in { 234 def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst), 235 "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>, 236 OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; 237 def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst), 238 "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>, 239 OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, 240 Sched<[WriteJumpLd]>, NOTRACK; 241 def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst), 242 "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>, 243 OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; 244 def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst), 245 "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>, 246 OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>, 247 Sched<[WriteJumpLd]>, NOTRACK; 248 } 249 250 let Predicates = [Not64BitMode], AsmVariantName = "att" in { 251 def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), 252 (ins i16imm:$off, i16imm:$seg), 253 "lcall{w}\t$seg, $off", []>, 254 OpSize16, Sched<[WriteJump]>; 255 def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), 256 (ins i32imm:$off, i16imm:$seg), 257 "lcall{l}\t$seg, $off", []>, 258 OpSize32, Sched<[WriteJump]>; 259 } 260 261 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 262 "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; 263 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 264 "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; 265 } 266 267 268/* 269// Tail call stuff. 270let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 271 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 272 let Uses = [ESP, SSP] in { 273 def TCRETURNdi : PseudoI<(outs), 274 (ins i32imm_pcrel:$dst, i32imm:$offset), []>, NotMemoryFoldable; 275 def TCRETURNri : PseudoI<(outs), 276 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; 277 let mayLoad = 1 in 278 def TCRETURNmi : PseudoI<(outs), 279 (ins i32mem_TC:$dst, i32imm:$offset), []>; 280 281 // FIXME: The should be pseudo instructions that are lowered when going to 282 // mcinst. 283 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), 284 (ins i32imm_pcrel:$dst), "jmp\t$dst", []>; 285 286 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 287 "", []>; // FIXME: Remove encoding when JIT is dead. 288 let mayLoad = 1 in 289 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), 290 "jmp{l}\t{*}$dst", []>; 291} 292 293// Conditional tail calls are similar to the above, but they are branches 294// rather than barriers, and they use EFLAGS. 295let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, 296 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 297 let Uses = [ESP, EFLAGS, SSP] in { 298 def TCRETURNdicc : PseudoI<(outs), 299 (ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>; 300 301 // This gets substituted to a conditional jump instruction in MC lowering. 302 def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs), 303 (ins i32imm_pcrel:$dst, i32imm:$cond), "", []>; 304} 305*/ 306 307 308//===----------------------------------------------------------------------===// 309// Call Instructions... 310// 311 312// RSP is marked as a use to prevent stack-pointer assignments that appear 313// immediately before calls from potentially appearing dead. Uses for argument 314// registers are added manually. 315let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { 316 // NOTE: this pattern doesn't match "X86call imm", because we do not know 317 // that the offset between an arbitrary immediate and the call will fit in 318 // the 32-bit pcrel field that we have. 319 def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, 320 (outs), (ins i64i32imm_pcrel:$dst), 321 "call{q}\t$dst", []>, OpSize32, 322 Requires<[In64BitMode]>; 323 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), 324 "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, 325 Requires<[In64BitMode,NotUseRetpoline]>; 326 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), 327 "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, 328 Requires<[In64BitMode,FavorMemIndirectCall, 329 NotUseRetpoline]>; 330 331 // Non-tracking calls for IBT, use with caution. 332 let isCodeGenOnly = 1 in { 333 def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst), 334 "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>, 335 Requires<[In64BitMode]>, NOTRACK; 336 def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst), 337 "call{q}\t{*}$dst", 338 [(X86NoTrackCall(loadi64 addr : $dst))]>, 339 Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK; 340 } 341 342 def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst), 343 "lcall{q}\t{*}$dst", []>; 344} 345 346/* 347let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 348 isCodeGenOnly = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { 349 def TCRETURNdi64 : PseudoI<(outs), 350 (ins i64i32imm_pcrel:$dst, i32imm:$offset), 351 []>; 352 def TCRETURNri64 : PseudoI<(outs), 353 (ins ptr_rc_tailcall:$dst, i32imm:$offset), []>, NotMemoryFoldable; 354 let mayLoad = 1 in 355 def TCRETURNmi64 : PseudoI<(outs), 356 (ins i64mem_TC:$dst, i32imm:$offset), []>, NotMemoryFoldable; 357 358 def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), 359 "jmp\t$dst", []>; 360 361 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 362 "jmp{q}\t{*}$dst", []>; 363 364 let mayLoad = 1 in 365 def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 366 "jmp{q}\t{*}$dst", []>; 367 368 // Win64 wants indirect jumps leaving the function to have a REX_W prefix. 369 let hasREX_WPrefix = 1 in { 370 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), 371 "rex64 jmp{q}\t{*}$dst", []>; 372 373 let mayLoad = 1 in 374 def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), 375 "rex64 jmp{q}\t{*}$dst", []>; 376 } 377} 378 379let isPseudo = 1, isCall = 1, isCodeGenOnly = 1, 380 Uses = [RSP, SSP], 381 usesCustomInserter = 1, 382 SchedRW = [WriteJump] in { 383 def RETPOLINE_CALL32 : 384 PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>, 385 Requires<[Not64BitMode,UseRetpoline]>; 386 387 def RETPOLINE_CALL64 : 388 PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>, 389 Requires<[In64BitMode,UseRetpoline]>; 390 391 // Retpoline variant of indirect tail calls. 392 let isTerminator = 1, isReturn = 1, isBarrier = 1 in { 393 def RETPOLINE_TCRETURN64 : 394 PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>; 395 def RETPOLINE_TCRETURN32 : 396 PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>; 397 } 398} 399 400// Conditional tail calls are similar to the above, but they are branches 401// rather than barriers, and they use EFLAGS. 402let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, 403 isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in 404 let Uses = [RSP, EFLAGS, SSP] in { 405 def TCRETURNdi64cc : PseudoI<(outs), 406 (ins i64i32imm_pcrel:$dst, i32imm:$offset, 407 i32imm:$cond), []>; 408 409 // This gets substituted to a conditional jump instruction in MC lowering. 410 def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs), 411 (ins i64i32imm_pcrel:$dst, i32imm:$cond), "", []>; 412} 413*/ 414