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Searched refs:PLL0REFCLKSEL (Results 1 – 2 of 2) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/
H A Dwhiterabbit_gtpe2_channel_wrapper.vhd461 PLL0REFCLKSEL => "001",
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_xtra.v13796 input [2:0] PLL0REFCLKSEL; port