| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 611 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
693 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
694 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 663 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
745 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
746 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 663 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
745 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
746 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 663 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
745 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
746 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 663 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
745 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
746 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-tegra/tegra30/ |
| H A D | clock.c | 666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0) macro
748 value &= ~PLLE_BASE_MDIV(0xff); in tegra_plle_enable()
749 value |= PLLE_BASE_MDIV(m); in tegra_plle_enable()
|