1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 /* Tegra30 Clock control functions */
8
9 #include <common.h>
10 #include <errno.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/io.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
18 #include <div64.h>
19 #include <fdtdec.h>
20 #include <linux/delay.h>
21
22 /*
23 * Clock types that we can use as a source. The Tegra30 has muxes for the
24 * peripheral clocks, and in most cases there are four options for the clock
25 * source. This gives us a clock 'type' and exploits what commonality exists
26 * in the device.
27 *
28 * Letters are obvious, except for T which means CLK_M, and S which means the
29 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
30 * datasheet) and PLL_M are different things. The former is the basic
31 * clock supplied to the SOC from an external oscillator. The latter is the
32 * memory clock PLL.
33 *
34 * See definitions in clock_id in the header file.
35 */
36 enum clock_type_id {
37 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
38 CLOCK_TYPE_MCPA, /* and so on */
39 CLOCK_TYPE_MCPT,
40 CLOCK_TYPE_PCM,
41 CLOCK_TYPE_PCMT,
42 CLOCK_TYPE_PCMT16,
43 CLOCK_TYPE_PDCT,
44 CLOCK_TYPE_ACPT,
45 CLOCK_TYPE_ASPTE,
46 CLOCK_TYPE_PMDACD2T,
47 CLOCK_TYPE_PCST,
48
49 CLOCK_TYPE_COUNT,
50 CLOCK_TYPE_NONE = -1, /* invalid clock type */
51 };
52
53 enum {
54 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
55 };
56
57 /*
58 * Clock source mux for each clock type. This just converts our enum into
59 * a list of mux sources for use by the code.
60 *
61 * Note:
62 * The extra column in each clock source array is used to store the mask
63 * bits in its register for the source.
64 */
65 #define CLK(x) CLOCK_ID_ ## x
66 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
67 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
69 MASK_BITS_31_30},
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
72 MASK_BITS_31_30},
73 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
75 MASK_BITS_31_30},
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
78 MASK_BITS_31_30},
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
81 MASK_BITS_31_30},
82 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
84 MASK_BITS_31_30},
85 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
87 MASK_BITS_31_30},
88 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
90 MASK_BITS_31_30},
91 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
92 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
93 MASK_BITS_31_29},
94 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
95 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
96 MASK_BITS_31_29},
97 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
98 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
99 MASK_BITS_31_28}
100 };
101
102 /*
103 * Clock type for each peripheral clock source. We put the name in each
104 * record just so it is easy to match things up
105 */
106 #define TYPE(name, type) type
107 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
108 /* 0x00 */
109 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
110 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
111 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
112 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
113 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
114 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
115 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
116 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
117
118 /* 0x08 */
119 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
120 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
121 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
122 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
123 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
124 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
125 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
126 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
127
128 /* 0x10 */
129 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
130 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
131 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
132 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
133 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
134 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
135 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
136 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
137
138 /* 0x18 */
139 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
140 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
141 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
142 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
143 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
144 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
145 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
146 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
147
148 /* 0x20 */
149 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
150 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
151 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
152 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
153 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
154 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
155 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
156 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
157
158 /* 0x28 */
159 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
160 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
161 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
162 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
163 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
164 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
165 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
166 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
167
168 /* 0x30 */
169 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
170 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
171 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
172 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
173 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
174 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
175 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
176 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
177
178 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
179 TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
180 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
181 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
182 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
183 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
184 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
185 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
186 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
187
188 /* 0x40 */
189 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
190 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
191 TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
192 TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
193 TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
194 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
195 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
196 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
197
198 /* 0x48 */
199 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
200 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
201 TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
202 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
203 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
204 TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
205 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
206 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
207
208 /* 0x50 */
209 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
211 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
214 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
215 TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
216 };
217
218 /*
219 * This array translates a periph_id to a periphc_internal_id
220 *
221 * Not present/matched up:
222 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
223 * SPDIF - which is both 0x08 and 0x0c
224 *
225 */
226 #define NONE(name) (-1)
227 #define OFFSET(name, value) PERIPHC_ ## name
228 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
229 /* Low word: 31:0 */
230 NONE(CPU),
231 NONE(COP),
232 NONE(TRIGSYS),
233 NONE(RESERVED3),
234 NONE(RESERVED4),
235 NONE(TMR),
236 PERIPHC_UART1,
237 PERIPHC_UART2, /* and vfir 0x68 */
238
239 /* 8 */
240 NONE(GPIO),
241 PERIPHC_SDMMC2,
242 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
243 PERIPHC_I2S1,
244 PERIPHC_I2C1,
245 PERIPHC_NDFLASH,
246 PERIPHC_SDMMC1,
247 PERIPHC_SDMMC4,
248
249 /* 16 */
250 NONE(RESERVED16),
251 PERIPHC_PWM,
252 PERIPHC_I2S2,
253 PERIPHC_EPP,
254 PERIPHC_VI,
255 PERIPHC_G2D,
256 NONE(USBD),
257 NONE(ISP),
258
259 /* 24 */
260 PERIPHC_G3D,
261 NONE(RESERVED25),
262 PERIPHC_DISP2,
263 PERIPHC_DISP1,
264 PERIPHC_HOST1X,
265 NONE(VCP),
266 PERIPHC_I2S0,
267 NONE(CACHE2),
268
269 /* Middle word: 63:32 */
270 NONE(MEM),
271 NONE(AHBDMA),
272 NONE(APBDMA),
273 NONE(RESERVED35),
274 NONE(RESERVED36),
275 NONE(STAT_MON),
276 NONE(RESERVED38),
277 NONE(RESERVED39),
278
279 /* 40 */
280 NONE(KFUSE),
281 PERIPHC_SBC1,
282 PERIPHC_NOR,
283 NONE(RESERVED43),
284 PERIPHC_SBC2,
285 NONE(RESERVED45),
286 PERIPHC_SBC3,
287 PERIPHC_DVC_I2C,
288
289 /* 48 */
290 NONE(DSI),
291 PERIPHC_TVO, /* also CVE 0x40 */
292 PERIPHC_MIPI,
293 PERIPHC_HDMI,
294 NONE(CSI),
295 PERIPHC_TVDAC,
296 PERIPHC_I2C2,
297 PERIPHC_UART3,
298
299 /* 56 */
300 NONE(RESERVED56),
301 PERIPHC_EMC,
302 NONE(USB2),
303 NONE(USB3),
304 PERIPHC_MPE,
305 PERIPHC_VDE,
306 NONE(BSEA),
307 NONE(BSEV),
308
309 /* Upper word 95:64 */
310 PERIPHC_SPEEDO,
311 PERIPHC_UART4,
312 PERIPHC_UART5,
313 PERIPHC_I2C3,
314 PERIPHC_SBC4,
315 PERIPHC_SDMMC3,
316 NONE(PCIE),
317 PERIPHC_OWR,
318
319 /* 72 */
320 NONE(AFI),
321 PERIPHC_CSITE,
322 NONE(PCIEXCLK),
323 NONE(AVPUCQ),
324 NONE(RESERVED76),
325 NONE(RESERVED77),
326 NONE(RESERVED78),
327 NONE(DTV),
328
329 /* 80 */
330 PERIPHC_NANDSPEED,
331 PERIPHC_I2CSLOW,
332 NONE(DSIB),
333 NONE(RESERVED83),
334 NONE(IRAMA),
335 NONE(IRAMB),
336 NONE(IRAMC),
337 NONE(IRAMD),
338
339 /* 88 */
340 NONE(CRAM2),
341 NONE(RESERVED89),
342 NONE(MDOUBLER),
343 NONE(RESERVED91),
344 NONE(SUSOUT),
345 NONE(RESERVED93),
346 NONE(RESERVED94),
347 NONE(RESERVED95),
348
349 /* V word: 31:0 */
350 NONE(CPUG),
351 NONE(CPULP),
352 PERIPHC_G3D2,
353 PERIPHC_MSELECT,
354 PERIPHC_TSENSOR,
355 PERIPHC_I2S3,
356 PERIPHC_I2S4,
357 PERIPHC_I2C4,
358
359 /* 08 */
360 PERIPHC_SBC5,
361 PERIPHC_SBC6,
362 PERIPHC_AUDIO,
363 NONE(APBIF),
364 PERIPHC_DAM0,
365 PERIPHC_DAM1,
366 PERIPHC_DAM2,
367 PERIPHC_HDA2CODEC2X,
368
369 /* 16 */
370 NONE(ATOMICS),
371 NONE(RESERVED17),
372 NONE(RESERVED18),
373 NONE(RESERVED19),
374 NONE(RESERVED20),
375 NONE(RESERVED21),
376 NONE(RESERVED22),
377 PERIPHC_ACTMON,
378
379 /* 24 */
380 NONE(RESERVED24),
381 NONE(RESERVED25),
382 NONE(RESERVED26),
383 NONE(RESERVED27),
384 PERIPHC_SATA,
385 PERIPHC_HDA,
386 NONE(RESERVED30),
387 NONE(RESERVED31),
388
389 /* W word: 31:0 */
390 NONE(HDA2HDMICODEC),
391 NONE(SATACOLD),
392 NONE(RESERVED0_PCIERX0),
393 NONE(RESERVED1_PCIERX1),
394 NONE(RESERVED2_PCIERX2),
395 NONE(RESERVED3_PCIERX3),
396 NONE(RESERVED4_PCIERX4),
397 NONE(RESERVED5_PCIERX5),
398
399 /* 40 */
400 NONE(CEC),
401 NONE(RESERVED6_PCIE2),
402 NONE(RESERVED7_EMC),
403 NONE(RESERVED8_HDMI),
404 NONE(RESERVED9_SATA),
405 NONE(RESERVED10_MIPI),
406 NONE(EX_RESERVED46),
407 NONE(EX_RESERVED47),
408 };
409
410 /*
411 * PLL divider shift/mask tables for all PLL IDs.
412 */
413 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
414 /*
415 * T30: some deviations from T2x.
416 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
417 * If lock_ena or lock_det are >31, they're not used in that PLL.
418 */
419
420 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
421 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
422 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
423 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
424 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
425 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
426 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
427 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
428 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
429 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
430 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
431 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
432 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
433 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
434 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
435 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
436 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
437 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
438 };
439
440 /*
441 * Get the oscillator frequency, from the corresponding hardware configuration
442 * field. Note that T30 supports 3 new higher freqs, but we map back
443 * to the old T20 freqs. Support for the higher oscillators is TBD.
444 */
clock_get_osc_freq(void)445 enum clock_osc_freq clock_get_osc_freq(void)
446 {
447 struct clk_rst_ctlr *clkrst =
448 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
449 u32 reg;
450
451 reg = readl(&clkrst->crc_osc_ctrl);
452 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
453
454 if (reg & 1) /* one of the newer freqs */
455 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
456
457 return reg >> 2; /* Map to most common (T20) freqs */
458 }
459
460 /* Returns a pointer to the clock source register for a peripheral */
get_periph_source_reg(enum periph_id periph_id)461 u32 *get_periph_source_reg(enum periph_id periph_id)
462 {
463 struct clk_rst_ctlr *clkrst =
464 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
465 enum periphc_internal_id internal_id;
466
467 /* Coresight is a special case */
468 if (periph_id == PERIPH_ID_CSI)
469 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
470
471 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
472 internal_id = periph_id_to_internal_id[periph_id];
473 assert(internal_id != -1);
474 if (internal_id >= PERIPHC_VW_FIRST) {
475 internal_id -= PERIPHC_VW_FIRST;
476 return &clkrst->crc_clk_src_vw[internal_id];
477 } else
478 return &clkrst->crc_clk_src[internal_id];
479 }
480
get_periph_clock_info(enum periph_id periph_id,int * mux_bits,int * divider_bits,int * type)481 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
482 int *divider_bits, int *type)
483 {
484 enum periphc_internal_id internal_id;
485
486 if (!clock_periph_id_isvalid(periph_id))
487 return -1;
488
489 internal_id = periph_id_to_internal_id[periph_id];
490 if (!periphc_internal_id_isvalid(internal_id))
491 return -1;
492
493 *type = clock_periph_type[internal_id];
494 if (!clock_type_id_isvalid(*type))
495 return -1;
496
497 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
498
499 if (*type == CLOCK_TYPE_PCMT16)
500 *divider_bits = 16;
501 else
502 *divider_bits = 8;
503
504 return 0;
505 }
506
get_periph_clock_id(enum periph_id periph_id,int source)507 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
508 {
509 enum periphc_internal_id internal_id;
510 int type;
511
512 if (!clock_periph_id_isvalid(periph_id))
513 return CLOCK_ID_NONE;
514
515 internal_id = periph_id_to_internal_id[periph_id];
516 if (!periphc_internal_id_isvalid(internal_id))
517 return CLOCK_ID_NONE;
518
519 type = clock_periph_type[internal_id];
520 if (!clock_type_id_isvalid(type))
521 return CLOCK_ID_NONE;
522
523 return clock_source[type][source];
524 }
525
526 /**
527 * Given a peripheral ID and the required source clock, this returns which
528 * value should be programmed into the source mux for that peripheral.
529 *
530 * There is special code here to handle the one source type with 5 sources.
531 *
532 * @param periph_id peripheral to start
533 * @param source PLL id of required parent clock
534 * @param mux_bits Set to number of bits in mux register: 2 or 4
535 * @param divider_bits Set to number of divider bits (8 or 16)
536 * @return mux value (0-4, or -1 if not found)
537 */
get_periph_clock_source(enum periph_id periph_id,enum clock_id parent,int * mux_bits,int * divider_bits)538 int get_periph_clock_source(enum periph_id periph_id,
539 enum clock_id parent, int *mux_bits, int *divider_bits)
540 {
541 enum clock_type_id type;
542 int mux, err;
543
544 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
545 assert(!err);
546
547 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
548 if (clock_source[type][mux] == parent)
549 return mux;
550
551 /* if we get here, either us or the caller has made a mistake */
552 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
553 parent);
554 return -1;
555 }
556
clock_set_enable(enum periph_id periph_id,int enable)557 void clock_set_enable(enum periph_id periph_id, int enable)
558 {
559 struct clk_rst_ctlr *clkrst =
560 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
561 u32 *clk;
562 u32 reg;
563
564 /* Enable/disable the clock to this peripheral */
565 assert(clock_periph_id_isvalid(periph_id));
566 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
567 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
568 else
569 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
570 reg = readl(clk);
571 if (enable)
572 reg |= PERIPH_MASK(periph_id);
573 else
574 reg &= ~PERIPH_MASK(periph_id);
575 writel(reg, clk);
576 }
577
reset_set_enable(enum periph_id periph_id,int enable)578 void reset_set_enable(enum periph_id periph_id, int enable)
579 {
580 struct clk_rst_ctlr *clkrst =
581 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
582 u32 *reset;
583 u32 reg;
584
585 /* Enable/disable reset to the peripheral */
586 assert(clock_periph_id_isvalid(periph_id));
587 if (periph_id < PERIPH_ID_VW_FIRST)
588 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
589 else
590 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
591 reg = readl(reset);
592 if (enable)
593 reg |= PERIPH_MASK(periph_id);
594 else
595 reg &= ~PERIPH_MASK(periph_id);
596 writel(reg, reset);
597 }
598
599 #if CONFIG_IS_ENABLED(OF_CONTROL)
600 /*
601 * Convert a device tree clock ID to our peripheral ID. They are mostly
602 * the same but we are very cautious so we check that a valid clock ID is
603 * provided.
604 *
605 * @param clk_id Clock ID according to tegra30 device tree binding
606 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
607 */
clk_id_to_periph_id(int clk_id)608 enum periph_id clk_id_to_periph_id(int clk_id)
609 {
610 if (clk_id > PERIPH_ID_COUNT)
611 return PERIPH_ID_NONE;
612
613 switch (clk_id) {
614 case PERIPH_ID_RESERVED3:
615 case PERIPH_ID_RESERVED4:
616 case PERIPH_ID_RESERVED16:
617 case PERIPH_ID_RESERVED24:
618 case PERIPH_ID_RESERVED35:
619 case PERIPH_ID_RESERVED43:
620 case PERIPH_ID_RESERVED45:
621 case PERIPH_ID_RESERVED56:
622 case PERIPH_ID_PCIEXCLK:
623 case PERIPH_ID_RESERVED76:
624 case PERIPH_ID_RESERVED77:
625 case PERIPH_ID_RESERVED78:
626 case PERIPH_ID_RESERVED83:
627 case PERIPH_ID_RESERVED89:
628 case PERIPH_ID_RESERVED91:
629 case PERIPH_ID_RESERVED93:
630 case PERIPH_ID_RESERVED94:
631 case PERIPH_ID_RESERVED95:
632 return PERIPH_ID_NONE;
633 default:
634 return clk_id;
635 }
636 }
637 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
638
clock_early_init(void)639 void clock_early_init(void)
640 {
641 tegra30_set_up_pllp();
642 }
643
arch_timer_init(void)644 void arch_timer_init(void)
645 {
646 }
647
648 #define PMC_SATA_PWRGT 0x1ac
649 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
650 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
651
652 #define PLLE_SS_CNTL 0x68
653 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
654 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
655 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
656 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
657 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
658 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
659
660 #define PLLE_BASE 0x0e8
661 #define PLLE_BASE_ENABLE_CML (1 << 31)
662 #define PLLE_BASE_ENABLE (1 << 30)
663 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
664 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
665 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
666 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
667
668 #define PLLE_MISC 0x0ec
669 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
670 #define PLLE_MISC_PLL_READY (1 << 15)
671 #define PLLE_MISC_LOCK (1 << 11)
672 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
673 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
674
tegra_plle_train(void)675 static int tegra_plle_train(void)
676 {
677 unsigned int timeout = 2000;
678 unsigned long value;
679
680 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
681 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
682 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
683
684 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
685 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
686 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
687
688 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
689 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
690 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
691
692 do {
693 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
694 if (value & PLLE_MISC_PLL_READY)
695 break;
696
697 udelay(100);
698 } while (--timeout);
699
700 if (timeout == 0) {
701 pr_err("timeout waiting for PLLE to become ready");
702 return -ETIMEDOUT;
703 }
704
705 return 0;
706 }
707
tegra_plle_enable(void)708 int tegra_plle_enable(void)
709 {
710 unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
711 u32 value;
712 int err;
713
714 /* disable PLLE clock */
715 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
716 value &= ~PLLE_BASE_ENABLE_CML;
717 value &= ~PLLE_BASE_ENABLE;
718 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
719
720 /* clear lock enable and setup field */
721 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
722 value &= ~PLLE_MISC_LOCK_ENABLE;
723 value &= ~PLLE_MISC_SETUP_BASE(0xffff);
724 value &= ~PLLE_MISC_SETUP_EXT(0x3);
725 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
726
727 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
728 if ((value & PLLE_MISC_PLL_READY) == 0) {
729 err = tegra_plle_train();
730 if (err < 0) {
731 pr_err("failed to train PLLE: %d", err);
732 return err;
733 }
734 }
735
736 /* configure PLLE */
737 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
738
739 value &= ~PLLE_BASE_PLDIV_CML(0x0f);
740 value |= PLLE_BASE_PLDIV_CML(cpcon);
741
742 value &= ~PLLE_BASE_PLDIV(0x3f);
743 value |= PLLE_BASE_PLDIV(p);
744
745 value &= ~PLLE_BASE_NDIV(0xff);
746 value |= PLLE_BASE_NDIV(n);
747
748 value &= ~PLLE_BASE_MDIV(0xff);
749 value |= PLLE_BASE_MDIV(m);
750
751 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
752
753 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
754 value |= PLLE_MISC_SETUP_BASE(0x7);
755 value |= PLLE_MISC_LOCK_ENABLE;
756 value |= PLLE_MISC_SETUP_EXT(0);
757 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
758
759 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
760 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
761 PLLE_SS_CNTL_BYPASS_SS;
762 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
763
764 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
765 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
766 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
767
768 do {
769 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
770 if (value & PLLE_MISC_LOCK)
771 break;
772
773 udelay(2);
774 } while (--timeout);
775
776 if (timeout == 0) {
777 pr_err("timeout waiting for PLLE to lock");
778 return -ETIMEDOUT;
779 }
780
781 udelay(50);
782
783 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
784 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
785 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
786
787 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
788 value |= PLLE_SS_CNTL_SSCINC(0x01);
789
790 value &= ~PLLE_SS_CNTL_SSCBYP;
791 value &= ~PLLE_SS_CNTL_INTERP_RESET;
792 value &= ~PLLE_SS_CNTL_BYPASS_SS;
793
794 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
795 value |= PLLE_SS_CNTL_SSCMAX(0x24);
796 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
797
798 return 0;
799 }
800
801 struct periph_clk_init periph_clk_init_table[] = {
802 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
803 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
804 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
805 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
806 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
807 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
808 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
809 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
810 { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
811 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
812 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
813 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
814 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
815 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
816 { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
817 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
818 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
819 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
820 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
821 { -1, },
822 };
823