| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 553 #define PMC_SATA_PWRGT 0x1ac macro
585 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
587 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
589 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
591 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
593 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
595 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 616 #define PMC_SATA_PWRGT 0x1ac macro
648 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
650 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
652 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
654 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
656 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
658 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 616 #define PMC_SATA_PWRGT 0x1ac macro
648 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
650 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
652 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
654 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
656 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
658 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 616 #define PMC_SATA_PWRGT 0x1ac macro
648 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
650 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
652 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
654 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
656 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
658 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 616 #define PMC_SATA_PWRGT 0x1ac macro
648 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
650 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
652 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
654 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
656 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
658 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-tegra/tegra20/ |
| H A D | clock.c | 619 #define PMC_SATA_PWRGT 0x1ac macro
651 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
653 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
655 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
657 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
659 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
661 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT); in tegra_plle_train()
|