| /dports/cad/digital/Digital-0.27/src/main/resources/verilog/ |
| H A D | DIG_DCM_SP.v | 53 .PSCLK(1'b0), // 1-bit input: Phase shift clock input
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| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-sha256crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 121 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .PSDONE(),
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-sha512crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 121 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .PSDONE(),
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-md5crypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 121 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .PSDONE(),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/top/USRP2/ |
| H A D | u2_rev3.v | 244 .PSCLK(0),
414 .PSCLK(1'b0),
463 .PSCLK(1'b0),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b200/coregen/ |
| H A D | b200_clk_gen.v | 130 .PSCLK (1'b0),
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| H A D | b200_clk_gen.xco | 232 CSET psclk_port=PSCLK
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_mmcm.v | 88 .PSCLK (1'b0),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/ip/one_gig_eth_pcs_pma/ |
| H A D | one_gig_eth_pcs_pma_clocking.v | 147 .PSCLK (1'b0),
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-bcrypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 116 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .PSDONE(),
|
| H A D | cmt_common.v | 71 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .PSDONE(),
|
| /dports/security/john/john-1.9.0-jumbo-1/src/ztex/fpga-descrypt/ztex_inouttraffic/ |
| H A D | cmt2.v | 117 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .PSDONE(),
|
| H A D | cmt_common.v | 71 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), .PSDONE(),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/ |
| H A D | xwrc_platform_xilinx.vhd | 310 PSCLK => '0',
409 PSCLK => '0',
469 PSCLK => '0',
537 PSCLK => '0',
633 PSCLK => '0',
694 -- PSCLK => '0',
771 PSCLK => '0',
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ |
| H A D | e320_clocking.v | 167 .PSCLK (1'b0),
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| /dports/cad/digital/Digital-0.27/src/main/resources/vhdl/ |
| H A D | DIG_DCM_SP.tem | 48 PSCLK => '0', -- 1-bit input: Phase shift clock input
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/models/ |
| H A D | DCM_SP.v | 35 CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
61 input PSCLK, PSEN, PSINCDEC, RST; port
364 buf b_psclk (psclk_in, PSCLK);
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/e320/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_x1.v | 232 .PSCLK (1'b0),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/ip/aurora_64b66b_pcs_pma/ |
| H A D | aurora_phy_x1.v | 232 .PSCLK (1'b0),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/b2xxmini/coregen/ |
| H A D | b205_clk_gen.xco | 232 CSET psclk_port=PSCLK
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/coregen/ |
| H A D | pll_100_40_75.xco | 232 CSET psclk_port=PSCLK
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/rh/db_ifc/ |
| H A D | RadioClocking.vhd | 184 PSCLK => PsClk,
|
| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp2/top/N2x0/ |
| H A D | u2plus.v | 207 .PSCLK(0),
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| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/n3xx/dboards/mg/db_ifc/ |
| H A D | RadioClocking.vhd | 183 PSCLK => PsClk,
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/ |
| H A D | cells_xtra.v | 7521 input PSCLK; port
7558 input PSCLK; port
7634 input PSCLK; port
7705 input PSCLK; port
7920 input PSCLK; port
8064 input PSCLK; port
8321 input PSCLK; port
8568 input PSCLK; port
31301 inout PSCLK; port
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