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Searched refs:Pow2MinusOne (Results 1 – 25 of 48) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4946 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4947 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4952 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4953 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp10438 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
10443 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4825 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4826 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp4825 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4826 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4946 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4947 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp4952 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4953 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp10470 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
10475 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp4953 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4954 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp9709 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
9714 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4825 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4826 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4953 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4954 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp9709 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
9714 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4825 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4826 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4825 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4826 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4953 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4954 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp9709 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
9714 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4946 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4947 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp4899 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4900 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp9011 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
9016 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp4895 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4896 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp8874 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
8879 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/
H A DAArch64FastISel.cpp4860 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4861 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne); in selectSDiv()
H A DAArch64ISelLowering.cpp8630 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT); in BuildSDIVPow2() local
8635 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4825 int64_t Pow2MinusOne = (1ULL << Lg2) - 1; in selectSDiv() local
4826 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, Pow2MinusOne); in selectSDiv()

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