RCC_CFGR_PLLSRC_PREDIV1 (reference) in projects: dports

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Searched refs:RCC_CFGR_PLLSRC_PREDIV1 (Results 1 – 16 of 16) sorted by relevance

/dports/devel/tinygo/tinygo-0.14.1/lib/CMSIS/Device/_Template_Flash/Test/
H A D	system_stm32f10x.c	627 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo24() 646 …RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 \| RCC_CFGR_PLLXTPRE_PREDIV1_Div2 \| RCC_CFGR_PLLMUL… in SetSysClockTo24() 730 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo36() 846 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo48() 947 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo56() 1050 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo72()
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A D	system_stm32f10x.c	452 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo24() 556 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo36() 677 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo48() 783 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo56() 891 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo72() 1005 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockToEXT_HSE_PLL()
H A D	stm32f10x.h	`1556 …#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selec… macro`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f10x/
H A D	system_stm32f10x.c	452 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo24() 556 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo36() 677 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo48() 783 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo56() 891 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockTo72() 1005 RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLSRC_PREDIV1 \| in SetSysClockToEXT_HSE_PLL()
H A D	stm32f10x.h	`1556 …#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selec… macro`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f0xx/
H A D	system_stm32f0xx.c	`321 … RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 \| RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLMULL6); in SetSysClock()`
H A D	stm32f0xx.h	`3983 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selec… macro`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A D	system_stm32f37x.c	`342 … RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 \| RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLMULL9); in SetSysClock()`
H A D	stm32f37x.h	`3775 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selec… macro`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f30x/
H A D	system_stm32f30x.c	`332 … RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 \| RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLMULL9); in SetSysClock()`
H A D	stm32f30x.h	`7296 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selec… macro`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/CMSIS/CM3_f37x/
H A D	system_stm32f37x.c	`342 … RCC->CFGR \|= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 \| RCC_CFGR_PLLXTPRE_PREDIV1 \| RCC_CFGR_PLLMULL9); in SetSysClock()`
H A D	stm32f37x.h	`3775 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selec… macro`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/eurorack/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A D	stm32f37x_rcc.h	`91 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F37x_StdPeriph_Driver/inc/
H A D	stm32f37x_rcc.h	`91 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1`
/dports/audio/lenticular-lv2/lenticular_lv2-0.5.0-14-g14d8075/parasites/stmlib/third_party/STM/STM32F30x_StdPeriph_Driver/inc/
H A D	stm32f30x_rcc.h	`102 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1`