1 /** 2 ****************************************************************************** 3 * @file stm32f0xx.h 4 * @author MCD Application Team 5 * @version V1.5.0 6 * @date 05-December-2014 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 8 * This file contains all the peripheral register's definitions, bits 9 * definitions and memory mapping for STM32F0xx devices. 10 * 11 * The file is the unique include file that the application programmer 12 * is using in the C source code, usually in main.c. This file contains: 13 * - Configuration section that allows to select: 14 * - The device used in the target application 15 * - To use or not the peripheral’s drivers in application code(i.e. 16 * code will be based on direct access to peripheral’s registers 17 * rather than drivers API), this option is controlled by 18 * "#define USE_STDPERIPH_DRIVER" 19 * - To change few application-specific parameters such as the HSE 20 * crystal frequency 21 * - Data structures and the address mapping for all peripherals 22 * - Peripheral's registers declarations and bits definition 23 * - Macros to access peripheral’s registers hardware 24 * 25 ****************************************************************************** 26 * @attention 27 * 28 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 29 * 30 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 31 * You may not use this file except in compliance with the License. 32 * You may obtain a copy of the License at: 33 * 34 * http://www.st.com/software_license_agreement_liberty_v2 35 * 36 * Unless required by applicable law or agreed to in writing, software 37 * distributed under the License is distributed on an "AS IS" BASIS, 38 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 39 * See the License for the specific language governing permissions and 40 * limitations under the License. 41 * 42 ****************************************************************************** 43 */ 44 45 /** @addtogroup CMSIS 46 * @{ 47 */ 48 49 /** @addtogroup stm32f0xx 50 * @{ 51 */ 52 53 #ifndef __STM32F0XX_H 54 #define __STM32F0XX_H 55 56 #ifdef __cplusplus 57 extern "C" { 58 #endif 59 60 /** @addtogroup Library_configuration_section 61 * @{ 62 */ 63 64 /* Uncomment the line below according to the target STM32F0 device used in your 65 application 66 */ 67 68 #if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && \ 69 !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091) && \ 70 !defined (STM32F070xB) && !defined (STM32F070x6) && !defined (STM32F030xC) 71 /* #define STM32F030 */ 72 /* #define STM32F031 */ 73 /* #define STM32F051 */ 74 /* #define STM32F072 */ 75 /* #define STM32F070xB */ 76 /* #define STM32F042 */ 77 /* #define STM32F070x6 */ 78 /* #define STM32F091 */ 79 /* #define STM32F030xC */ 80 #endif /* STM32F030 || STM32F031 || STM32F051 || STM32F072 || STM32F042 || STM32F091 || 81 STM32F070xB || STM32F070x6 || STM32F030xC */ 82 83 /* Tip: To avoid modifying this file each time you need to switch between these 84 devices, you can define the device in your toolchain compiler preprocessor. 85 */ 86 87 /* Old STM32F0XX definition, maintained for legacy purpose */ 88 #if defined(STM32F0XX) || defined(STM32F0XX_MD) 89 #define STM32F051 90 #endif /* STM32F0XX */ 91 92 /* Old STM32F0XX_LD definition, maintained for legacy purpose */ 93 #ifdef STM32F0XX_LD 94 #define STM32F031 95 #endif /* STM32F0XX_LD */ 96 97 /* Old STM32F0XX_HD definition, maintained for legacy purpose */ 98 #ifdef STM32F0XX_HD 99 #define STM32F072 100 #endif /* STM32F0XX_HD */ 101 102 /* Old STM32F030X6/X8 definition, maintained for legacy purpose */ 103 #if defined (STM32F030X8) || defined (STM32F030X6) 104 #define STM32F030 105 #endif /* STM32F030X8 or STM32F030X6 */ 106 107 108 #if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && \ 109 !defined (STM32F072) && !defined (STM32F042) && !defined (STM32F091) && \ 110 !defined (STM32F070xB) && !defined (STM32F070x6) && !defined (STM32F030xC) 111 #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)" 112 #endif /* STM32F030 || STM32F031 || STM32F051 || STM32F072 || STM32F042 || STM32F091 || 113 STM32F070xB || STM32F070x6 || STM32F030xC */ 114 115 #if !defined USE_STDPERIPH_DRIVER 116 /** 117 * @brief Comment the line below if you will not use the peripherals drivers. 118 In this case, these drivers will not be included and the application code will 119 be based on direct access to peripherals registers 120 */ 121 /*#define USE_STDPERIPH_DRIVER*/ 122 #endif /* USE_STDPERIPH_DRIVER */ 123 124 /** 125 * @brief In the following line adjust the value of External High Speed oscillator (HSE) 126 used in your application 127 128 Tip: To avoid modifying this file each time you need to use different HSE, you 129 can define the HSE value in your toolchain compiler preprocessor. 130 */ 131 #if !defined (HSE_VALUE) 132 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ 133 #endif /* HSE_VALUE */ 134 135 /** 136 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 137 Timeout value 138 */ 139 #if !defined (HSE_STARTUP_TIMEOUT) 140 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ 141 #endif /* HSE_STARTUP_TIMEOUT */ 142 143 /** 144 * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 145 Timeout value 146 */ 147 #if !defined (HSI_STARTUP_TIMEOUT) 148 #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ 149 #endif /* HSI_STARTUP_TIMEOUT */ 150 151 #if !defined (HSI_VALUE) 152 #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz. 153 The real value may vary depending on the variations 154 in voltage and temperature. */ 155 #endif /* HSI_VALUE */ 156 157 #if !defined (HSI14_VALUE) 158 #define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. 159 The real value may vary depending on the variations 160 in voltage and temperature. */ 161 #endif /* HSI14_VALUE */ 162 163 #if !defined (HSI48_VALUE) 164 #define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. 165 The real value may vary depending on the variations 166 in voltage and temperature. */ 167 #endif /* HSI48_VALUE */ 168 169 #if !defined (LSI_VALUE) 170 #define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz 171 The real value may vary depending on the variations 172 in voltage and temperature. */ 173 #endif /* LSI_VALUE */ 174 175 #if !defined (LSE_VALUE) 176 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ 177 #endif /* LSE_VALUE */ 178 179 /** 180 * @brief STM32F0xx Standard Peripheral Library version number V1.4.0 181 */ 182 #define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ 183 #define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ 184 #define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ 185 #define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 186 #define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\ 187 |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\ 188 |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\ 189 |(__STM32F0XX_STDPERIPH_VERSION_RC)) 190 191 /** 192 * @} 193 */ 194 195 /** @addtogroup Configuration_section_for_CMSIS 196 * @{ 197 */ 198 199 /** 200 * @brief STM32F0xx Interrupt Number Definition, according to the selected device 201 * in @ref Library_configuration_section 202 */ 203 #define __CM0_REV 0 /*!< Core Revision r0p0 */ 204 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ 205 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ 206 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 207 208 /*!< Interrupt Number Definition */ 209 typedef enum IRQn 210 { 211 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ 212 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 213 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ 214 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ 215 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ 216 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ 217 218 #if defined (STM32F051) 219 /****** STM32F051 specific Interrupt Numbers *************************************/ 220 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 221 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ 222 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 223 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 224 RCC_IRQn = 4, /*!< RCC Interrupt */ 225 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 226 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 227 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 228 TS_IRQn = 8, /*!< Touch sense controller Interrupt */ 229 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 230 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 231 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ 232 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ 233 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 234 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 235 TIM2_IRQn = 15, /*!< TIM2 Interrupt */ 236 TIM3_IRQn = 16, /*!< TIM3 Interrupt */ 237 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ 238 TIM14_IRQn = 19, /*!< TIM14 Interrupt */ 239 TIM15_IRQn = 20, /*!< TIM15 Interrupt */ 240 TIM16_IRQn = 21, /*!< TIM16 Interrupt */ 241 TIM17_IRQn = 22, /*!< TIM17 Interrupt */ 242 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 243 I2C2_IRQn = 24, /*!< I2C2 Interrupt */ 244 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 245 SPI2_IRQn = 26, /*!< SPI2 Interrupt */ 246 USART1_IRQn = 27, /*!< USART1 Interrupt */ 247 USART2_IRQn = 28, /*!< USART2 Interrupt */ 248 CEC_IRQn = 30 /*!< CEC Interrupt */ 249 #elif defined (STM32F031) 250 /****** STM32F031 specific Interrupt Numbers *************************************/ 251 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 252 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ 253 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 254 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 255 RCC_IRQn = 4, /*!< RCC Interrupt */ 256 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 257 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 258 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 259 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 260 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 261 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ 262 ADC1_IRQn = 12, /*!< ADC1 Interrupt */ 263 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 264 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 265 TIM2_IRQn = 15, /*!< TIM2 Interrupt */ 266 TIM3_IRQn = 16, /*!< TIM3 Interrupt */ 267 TIM14_IRQn = 19, /*!< TIM14 Interrupt */ 268 TIM16_IRQn = 21, /*!< TIM16 Interrupt */ 269 TIM17_IRQn = 22, /*!< TIM17 Interrupt */ 270 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 271 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 272 USART1_IRQn = 27 /*!< USART1 Interrupt */ 273 #elif defined (STM32F030) 274 /****** STM32F030 specific Interrupt Numbers *************************************/ 275 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 276 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 277 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 278 RCC_IRQn = 4, /*!< RCC Interrupt */ 279 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 280 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 281 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 282 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 283 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 284 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ 285 ADC1_IRQn = 12, /*!< ADC1 Interrupt */ 286 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 287 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 288 TIM3_IRQn = 16, /*!< TIM3 Interrupt */ 289 TIM14_IRQn = 19, /*!< TIM14 Interrupt */ 290 TIM15_IRQn = 20, /*!< TIM15 Interrupt */ 291 TIM16_IRQn = 21, /*!< TIM16 Interrupt */ 292 TIM17_IRQn = 22, /*!< TIM17 Interrupt */ 293 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 294 I2C2_IRQn = 24, /*!< I2C2 Interrupt */ 295 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 296 SPI2_IRQn = 26, /*!< SPI2 Interrupt */ 297 USART1_IRQn = 27, /*!< USART1 Interrupt */ 298 USART2_IRQn = 28 /*!< USART2 Interrupt */ 299 #elif defined (STM32F072) 300 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 301 PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ 302 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 303 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 304 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ 305 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 306 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 307 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 308 TSC_IRQn = 8, /*!< TSC Interrupt */ 309 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 310 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 311 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ 312 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ 313 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 314 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 315 TIM2_IRQn = 15, /*!< TIM2 Interrupt */ 316 TIM3_IRQn = 16, /*!< TIM3 Interrupt */ 317 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ 318 TIM7_IRQn = 18, /*!< TIM7 Interrupts */ 319 TIM14_IRQn = 19, /*!< TIM14 Interrupt */ 320 TIM15_IRQn = 20, /*!< TIM15 Interrupt */ 321 TIM16_IRQn = 21, /*!< TIM16 Interrupt */ 322 TIM17_IRQn = 22, /*!< TIM17 Interrupt */ 323 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 324 I2C2_IRQn = 24, /*!< I2C2 Interrupt */ 325 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 326 SPI2_IRQn = 26, /*!< SPI2 Interrupt */ 327 USART1_IRQn = 27, /*!< USART1 Interrupt */ 328 USART2_IRQn = 28, /*!< USART2 Interrupt */ 329 USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */ 330 CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ 331 USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ 332 #elif defined (STM32F042) 333 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 334 PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */ 335 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 336 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 337 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ 338 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 339 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 340 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 341 TSC_IRQn = 8, /*!< TSC Interrupt */ 342 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 343 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 344 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */ 345 ADC1_IRQn = 12, /*!< ADC1 Interrupts */ 346 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 347 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 348 TIM2_IRQn = 15, /*!< TIM2 Interrupt */ 349 TIM3_IRQn = 16, /*!< TIM3 Interrupt */ 350 TIM14_IRQn = 19, /*!< TIM14 Interrupt */ 351 TIM16_IRQn = 21, /*!< TIM16 Interrupt */ 352 TIM17_IRQn = 22, /*!< TIM17 Interrupt */ 353 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 354 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 355 SPI2_IRQn = 26, /*!< SPI2 Interrupt */ 356 USART1_IRQn = 27, /*!< USART1 Interrupt */ 357 USART2_IRQn = 28, /*!< USART2 Interrupt */ 358 CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */ 359 USB_IRQn = 31 /*!< USB Low Priority global Interrupt */ 360 #elif defined (STM32F091) 361 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 362 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */ 363 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 364 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 365 RCC_CRS_IRQn = 4, /*!< RCC & CRS Global Interrupts */ 366 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 367 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 368 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 369 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ 370 DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 371 DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */ 372 DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */ 373 ADC1_COMP_IRQn = 12, /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22) */ 374 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 375 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 376 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ 377 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 378 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */ 379 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ 380 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 381 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ 382 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 383 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 384 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 385 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */ 386 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 387 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ 388 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 389 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ 390 USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupts */ 391 CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ 392 #elif defined (STM32F070xB) 393 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 394 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 395 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 396 RCC_IRQn = 4, /*!< RCC Global Interrupts */ 397 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 398 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 399 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 400 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 401 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 402 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ 403 ADC1_IRQn = 12, /*!< ADC1 interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ 404 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 405 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 406 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 407 TIM6_IRQn = 17, /*!< TIM6 global Interrupts */ 408 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ 409 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 410 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ 411 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 412 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 413 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 414 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ 415 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 416 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ 417 USART1_IRQn = 27, /*!< USART1 global Interrupt */ 418 USART2_IRQn = 28, /*!< USART2 global Interrupt */ 419 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */ 420 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */ 421 #elif defined (STM32F070x6) 422 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 423 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 424 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 425 RCC_IRQn = 4, /*!< RCC Global Interrupts */ 426 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 427 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 428 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 429 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 430 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 431 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ 432 ADC1_IRQn = 12, /*!< ADC1 Interrupt */ 433 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 434 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 435 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 436 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 437 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 438 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 439 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 440 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 441 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 442 USART2_IRQn = 28, /*!< USART2 global Interrupt */ 443 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */ 444 #elif defined (STM32F030xC) 445 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 446 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ 447 FLASH_IRQn = 3, /*!< FLASH global Interrupt */ 448 RCC_IRQn = 4, /*!< RCC Global Interrupts */ 449 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 450 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 451 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 452 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 453 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 454 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */ 455 ADC1_IRQn = 12, /*!< ADC Interrupts */ 456 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ 457 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ 458 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ 459 TIM6_IRQn = 17, /*!< TIM6 global Interrupts */ 460 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ 461 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ 462 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ 463 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ 464 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ 465 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ 466 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ 467 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ 468 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ 469 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ 470 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ 471 USART3_6_IRQn = 29, /*!< USART3 to USART6 global Interrupts */ 472 #endif /* STM32F051 */ 473 }IRQn_Type; 474 475 /** 476 * @} 477 */ 478 479 #include "core_cm0.h" 480 #include "system_stm32f0xx.h" 481 #include <stdint.h> 482 483 /** @addtogroup Exported_types 484 * @{ 485 */ 486 487 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 488 489 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 490 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 491 492 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 493 494 /** @addtogroup Peripheral_registers_structures 495 * @{ 496 */ 497 498 /** 499 * @brief Analog to Digital Converter 500 */ 501 502 typedef struct 503 { 504 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ 505 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ 506 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ 507 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ 508 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ 509 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ 510 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 511 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 512 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ 513 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 514 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ 515 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 516 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ 517 } ADC_TypeDef; 518 519 typedef struct 520 { 521 __IO uint32_t CCR; 522 } ADC_Common_TypeDef; 523 524 525 /** 526 * @brief Controller Area Network TxMailBox 527 */ 528 typedef struct 529 { 530 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ 531 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ 532 __IO uint32_t TDLR; /*!< CAN mailbox data low register */ 533 __IO uint32_t TDHR; /*!< CAN mailbox data high register */ 534 } CAN_TxMailBox_TypeDef; 535 536 /** 537 * @brief Controller Area Network FIFOMailBox 538 */ 539 typedef struct 540 { 541 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ 542 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ 543 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ 544 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ 545 } CAN_FIFOMailBox_TypeDef; 546 547 /** 548 * @brief Controller Area Network FilterRegister 549 */ 550 typedef struct 551 { 552 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ 553 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ 554 } CAN_FilterRegister_TypeDef; 555 556 /** 557 * @brief Controller Area Network 558 */ 559 typedef struct 560 { 561 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ 562 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ 563 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ 564 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ 565 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ 566 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ 567 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ 568 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ 569 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ 570 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ 571 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ 572 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ 573 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ 574 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ 575 uint32_t RESERVED2; /*!< Reserved, 0x208 */ 576 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ 577 uint32_t RESERVED3; /*!< Reserved, 0x210 */ 578 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ 579 uint32_t RESERVED4; /*!< Reserved, 0x218 */ 580 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ 581 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ 582 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ 583 } CAN_TypeDef; 584 585 /** 586 * @brief HDMI-CEC 587 */ 588 589 typedef struct 590 { 591 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ 592 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ 593 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ 594 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ 595 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ 596 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ 597 }CEC_TypeDef; 598 599 /** 600 * @brief Comparator 601 */ 602 603 typedef struct 604 { 605 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */ 606 } COMP_TypeDef; 607 608 609 /** 610 * @brief CRC calculation unit 611 */ 612 613 typedef struct 614 { 615 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 616 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 617 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 618 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 619 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 620 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 621 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 622 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 623 } CRC_TypeDef; 624 625 /** 626 * @brief Clock Recovery System 627 */ 628 typedef struct 629 { 630 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ 631 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ 632 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ 633 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ 634 } CRS_TypeDef; 635 636 /** 637 * @brief Digital to Analog Converter 638 */ 639 640 typedef struct 641 { 642 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ 643 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ 644 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ 645 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ 646 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ 647 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ 648 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ 649 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ 650 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ 651 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ 652 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ 653 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ 654 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ 655 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ 656 } DAC_TypeDef; 657 658 /** 659 * @brief Debug MCU 660 */ 661 662 typedef struct 663 { 664 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 665 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 666 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 667 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 668 }DBGMCU_TypeDef; 669 670 /** 671 * @brief DMA Controller 672 */ 673 674 typedef struct 675 { 676 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 677 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 678 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 679 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 680 } DMA_Channel_TypeDef; 681 682 typedef struct 683 { 684 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 685 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 686 uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4*/ 687 __IO uint32_t RMPCR; /*!< Remap control register, Address offset: 0xA8 */ 688 }DMA_TypeDef; 689 690 /** 691 * @brief External Interrupt/Event Controller 692 */ 693 694 typedef struct 695 { 696 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 697 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 698 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 699 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 700 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 701 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 702 }EXTI_TypeDef; 703 704 /** 705 * @brief FLASH Registers 706 */ 707 typedef struct 708 { 709 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */ 710 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */ 711 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */ 712 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */ 713 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */ 714 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */ 715 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */ 716 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */ 717 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */ 718 } FLASH_TypeDef; 719 720 721 /** 722 * @brief Option Bytes Registers 723 */ 724 typedef struct 725 { 726 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ 727 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */ 728 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */ 729 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */ 730 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */ 731 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */ 732 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */ 733 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */ 734 } OB_TypeDef; 735 736 737 /** 738 * @brief General Purpose IO 739 */ 740 741 typedef struct 742 { 743 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 744 __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 745 uint16_t RESERVED0; /*!< Reserved, 0x06 */ 746 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 747 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 748 __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 749 uint16_t RESERVED1; /*!< Reserved, 0x12 */ 750 __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 751 uint16_t RESERVED2; /*!< Reserved, 0x16 */ 752 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 753 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 754 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ 755 __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 756 uint16_t RESERVED3; /*!< Reserved, 0x2A */ 757 }GPIO_TypeDef; 758 759 /** 760 * @brief SysTem Configuration 761 */ 762 763 typedef struct 764 { 765 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 766 uint32_t RESERVED; /*!< Reserved, 0x04 */ 767 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 768 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ 769 uint32_t RESERVED1[25]; /*!< Reserved + COMP, 0x1C */ 770 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */ 771 772 }SYSCFG_TypeDef; 773 774 /** 775 * @brief Inter-integrated Circuit Interface 776 */ 777 778 typedef struct 779 { 780 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 781 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 782 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 783 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 784 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 785 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 786 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 787 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 788 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 789 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 790 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 791 }I2C_TypeDef; 792 793 794 /** 795 * @brief Independent WATCHDOG 796 */ 797 typedef struct 798 { 799 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 800 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 801 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 802 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 803 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 804 } IWDG_TypeDef; 805 806 /** 807 * @brief Power Control 808 */ 809 810 typedef struct 811 { 812 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 813 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 814 } PWR_TypeDef; 815 816 817 /** 818 * @brief Reset and Clock Control 819 */ 820 typedef struct 821 { 822 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 823 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ 824 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ 825 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ 826 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ 827 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ 828 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ 829 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ 830 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ 831 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ 832 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ 833 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ 834 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ 835 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */ 836 } RCC_TypeDef; 837 838 /** 839 * @brief Real-Time Clock 840 */ 841 842 typedef struct 843 { 844 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 845 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 846 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 847 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 848 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 849 __IO uint32_t WUTR; /*!< RTC wakeup timer register,(only for STM32F072 devices) Address offset: 0x14 */ 850 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */ 851 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 852 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ 853 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 854 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 855 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 856 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 857 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 858 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 859 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 860 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ 861 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 862 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */ 863 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */ 864 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 865 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 866 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 867 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 868 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 869 } RTC_TypeDef; 870 871 /* Old register name definition maintained for legacy purpose */ 872 #define CAL CALR 873 874 /** 875 * @brief Serial Peripheral Interface 876 */ 877 878 typedef struct 879 { 880 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 881 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 882 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 883 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 884 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */ 885 uint16_t RESERVED2; /*!< Reserved, 0x0A */ 886 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ 887 uint16_t RESERVED3; /*!< Reserved, 0x0E */ 888 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 889 uint16_t RESERVED4; /*!< Reserved, 0x12 */ 890 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 891 uint16_t RESERVED5; /*!< Reserved, 0x16 */ 892 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 893 uint16_t RESERVED6; /*!< Reserved, 0x1A */ 894 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 895 uint16_t RESERVED7; /*!< Reserved, 0x1E */ 896 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 897 uint16_t RESERVED8; /*!< Reserved, 0x22 */ 898 } SPI_TypeDef; 899 900 901 /** 902 * @brief TIM 903 */ 904 typedef struct 905 { 906 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 907 uint16_t RESERVED0; /*!< Reserved, 0x02 */ 908 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 909 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 910 __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 911 uint16_t RESERVED2; /*!< Reserved, 0x0A */ 912 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 913 uint16_t RESERVED3; /*!< Reserved, 0x0E */ 914 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ 915 uint16_t RESERVED4; /*!< Reserved, 0x12 */ 916 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 917 uint16_t RESERVED5; /*!< Reserved, 0x16 */ 918 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 919 uint16_t RESERVED6; /*!< Reserved, 0x1A */ 920 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 921 uint16_t RESERVED7; /*!< Reserved, 0x1E */ 922 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 923 uint16_t RESERVED8; /*!< Reserved, 0x22 */ 924 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 925 __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 926 uint16_t RESERVED10; /*!< Reserved, 0x2A */ 927 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 928 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ 929 uint16_t RESERVED12; /*!< Reserved, 0x32 */ 930 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 931 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 932 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 933 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 934 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ 935 uint16_t RESERVED17; /*!< Reserved, 0x26 */ 936 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 937 uint16_t RESERVED18; /*!< Reserved, 0x4A */ 938 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 939 uint16_t RESERVED19; /*!< Reserved, 0x4E */ 940 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ 941 uint16_t RESERVED20; /*!< Reserved, 0x52 */ 942 } TIM_TypeDef; 943 944 /** 945 * @brief Touch Sensing Controller (TSC) 946 */ 947 typedef struct 948 { 949 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ 950 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ 951 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ 952 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ 953 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ 954 __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ 955 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ 956 __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ 957 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ 958 __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ 959 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ 960 __IO uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ 961 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ 962 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ 963 } TSC_TypeDef; 964 965 /** 966 * @brief Universal Synchronous Asynchronous Receiver Transmitter 967 */ 968 969 typedef struct 970 { 971 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 972 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 973 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 974 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 975 uint16_t RESERVED1; /*!< Reserved, 0x0E */ 976 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 977 uint16_t RESERVED2; /*!< Reserved, 0x12 */ 978 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 979 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ 980 uint16_t RESERVED3; /*!< Reserved, 0x1A */ 981 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 982 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 983 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 984 uint16_t RESERVED4; /*!< Reserved, 0x26 */ 985 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 986 uint16_t RESERVED5; /*!< Reserved, 0x2A */ 987 } USART_TypeDef; 988 989 990 /** 991 * @brief Window WATCHDOG 992 */ 993 typedef struct 994 { 995 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 996 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 997 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 998 } WWDG_TypeDef; 999 1000 1001 /** 1002 * @} 1003 */ 1004 1005 /** @addtogroup Peripheral_memory_map 1006 * @{ 1007 */ 1008 1009 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ 1010 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ 1011 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ 1012 1013 /*!< Peripheral memory map */ 1014 #define APBPERIPH_BASE PERIPH_BASE 1015 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000) 1016 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) 1017 1018 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000) 1019 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400) 1020 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000) 1021 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400) 1022 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000) 1023 #define RTC_BASE (APBPERIPH_BASE + 0x00002800) 1024 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00) 1025 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000) 1026 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800) 1027 #define USART2_BASE (APBPERIPH_BASE + 0x00004400) 1028 #define USART3_BASE (APBPERIPH_BASE + 0x00004800) 1029 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00) 1030 #define USART5_BASE (APBPERIPH_BASE + 0x00005000) 1031 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400) 1032 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800) 1033 #define CAN_BASE (APBPERIPH_BASE + 0x00006400) 1034 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00) 1035 #define PWR_BASE (APBPERIPH_BASE + 0x00007000) 1036 #define DAC_BASE (APBPERIPH_BASE + 0x00007400) 1037 #define CEC_BASE (APBPERIPH_BASE + 0x00007800) 1038 1039 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000) 1040 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C) 1041 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400) 1042 #define USART6_BASE (APBPERIPH_BASE + 0x00011400) 1043 #define USART7_BASE (APBPERIPH_BASE + 0x00011800) 1044 #define USART8_BASE (APBPERIPH_BASE + 0x00011C00) 1045 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400) /* KVL: TBC*/ 1046 #define ADC_BASE (APBPERIPH_BASE + 0x00012708) /* KVL: TBC*/ 1047 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00) 1048 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000) 1049 #define USART1_BASE (APBPERIPH_BASE + 0x00013800) 1050 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000) 1051 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400) 1052 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800) 1053 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800) 1054 1055 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000) 1056 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008) 1057 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C) 1058 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030) 1059 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044) 1060 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058) 1061 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C) 1062 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080) 1063 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400) 1064 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008) 1065 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C) 1066 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030) 1067 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044) 1068 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058) 1069 1070 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000) 1071 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */ 1072 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */ 1073 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000) 1074 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000) 1075 1076 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000) 1077 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400) 1078 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800) 1079 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00) 1080 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000) 1081 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400) 1082 1083 /** 1084 * @} 1085 */ 1086 1087 /** @addtogroup Peripheral_declaration 1088 * @{ 1089 */ 1090 1091 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 1092 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 1093 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 1094 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 1095 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 1096 #define RTC ((RTC_TypeDef *) RTC_BASE) 1097 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 1098 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 1099 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 1100 #define USART2 ((USART_TypeDef *) USART2_BASE) 1101 #define USART3 ((USART_TypeDef *) USART3_BASE) 1102 #define USART4 ((USART_TypeDef *) USART4_BASE) 1103 #define USART5 ((USART_TypeDef *) USART5_BASE) 1104 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 1105 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 1106 #define CAN ((CAN_TypeDef *) CAN_BASE) 1107 #define CRS ((CRS_TypeDef *) CRS_BASE) 1108 #define PWR ((PWR_TypeDef *) PWR_BASE) 1109 #define DAC ((DAC_TypeDef *) DAC_BASE) 1110 #define CEC ((CEC_TypeDef *) CEC_BASE) 1111 1112 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 1113 #define COMP ((COMP_TypeDef *) COMP_BASE) 1114 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 1115 #define USART6 ((USART_TypeDef *) USART6_BASE) 1116 #define USART7 ((USART_TypeDef *) USART7_BASE) 1117 #define USART8 ((USART_TypeDef *) USART8_BASE) 1118 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 1119 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) 1120 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 1121 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 1122 #define USART1 ((USART_TypeDef *) USART1_BASE) 1123 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 1124 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 1125 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 1126 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 1127 1128 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 1129 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 1130 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 1131 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 1132 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 1133 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 1134 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 1135 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 1136 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 1137 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 1138 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 1139 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 1140 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 1141 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 1142 1143 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 1144 #define OB ((OB_TypeDef *) OB_BASE) 1145 #define RCC ((RCC_TypeDef *) RCC_BASE) 1146 #define CRC ((CRC_TypeDef *) CRC_BASE) 1147 #define TSC ((TSC_TypeDef *) TSC_BASE) 1148 1149 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 1150 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 1151 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 1152 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 1153 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 1154 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 1155 1156 /** 1157 * @} 1158 */ 1159 1160 /** @addtogroup Exported_constants 1161 * @{ 1162 */ 1163 1164 /** @addtogroup Peripheral_Registers_Bits_Definition 1165 * @{ 1166 */ 1167 1168 /******************************************************************************/ 1169 /* Peripheral Registers Bits Definition */ 1170 /******************************************************************************/ 1171 /******************************************************************************/ 1172 /* */ 1173 /* Analog to Digital Converter (ADC) */ 1174 /* */ 1175 /******************************************************************************/ 1176 /******************** Bits definition for ADC_ISR register ******************/ 1177 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */ 1178 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */ 1179 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */ 1180 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */ 1181 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */ 1182 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */ 1183 1184 /* Old EOSEQ bit definition, maintained for legacy purpose */ 1185 #define ADC_ISR_EOS ADC_ISR_EOSEQ 1186 1187 /******************** Bits definition for ADC_IER register ******************/ 1188 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */ 1189 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */ 1190 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */ 1191 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */ 1192 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */ 1193 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */ 1194 1195 /* Old EOSEQIE bit definition, maintained for legacy purpose */ 1196 #define ADC_IER_EOSIE ADC_IER_EOSEQIE 1197 1198 /******************** Bits definition for ADC_CR register *******************/ 1199 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */ 1200 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */ 1201 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */ 1202 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */ 1203 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */ 1204 1205 /******************* Bits definition for ADC_CFGR1 register *****************/ 1206 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ 1207 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 1208 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 1209 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 1210 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 1211 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 1212 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ 1213 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */ 1214 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */ 1215 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */ 1216 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */ 1217 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */ 1218 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */ 1219 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ 1220 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 1221 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 1222 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ 1223 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */ 1224 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */ 1225 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */ 1226 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */ 1227 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */ 1228 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */ 1229 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */ 1230 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */ 1231 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */ 1232 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */ 1233 1234 /* Old WAIT bit definition, maintained for legacy purpose */ 1235 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT 1236 1237 /******************* Bits definition for ADC_CFGR2 register *****************/ 1238 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */ 1239 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */ 1240 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */ 1241 1242 /* Old bit definition, maintained for legacy purpose */ 1243 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */ 1244 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */ 1245 1246 /****************** Bit definition for ADC_SMPR register ********************/ 1247 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */ 1248 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 1249 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 1250 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */ 1251 1252 /* Old bit definition, maintained for legacy purpose */ 1253 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */ 1254 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */ 1255 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */ 1256 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */ 1257 1258 /******************* Bit definition for ADC_TR register ********************/ 1259 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */ 1260 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ 1261 1262 /* Old bit definition, maintained for legacy purpose */ 1263 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */ 1264 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */ 1265 1266 /****************** Bit definition for ADC_CHSELR register ******************/ 1267 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */ 1268 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */ 1269 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */ 1270 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */ 1271 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */ 1272 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */ 1273 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */ 1274 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */ 1275 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */ 1276 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */ 1277 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */ 1278 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */ 1279 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */ 1280 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */ 1281 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */ 1282 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */ 1283 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */ 1284 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */ 1285 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */ 1286 1287 /******************** Bit definition for ADC_DR register ********************/ 1288 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ 1289 1290 /******************* Bit definition for ADC_CCR register ********************/ 1291 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */ 1292 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */ 1293 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */ 1294 1295 /******************************************************************************/ 1296 /* */ 1297 /* Controller Area Network (CAN ) */ 1298 /* */ 1299 /******************************************************************************/ 1300 /******************* Bit definition for CAN_MCR register ********************/ 1301 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ 1302 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ 1303 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ 1304 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ 1305 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ 1306 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ 1307 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ 1308 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ 1309 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ 1310 1311 /******************* Bit definition for CAN_MSR register ********************/ 1312 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ 1313 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ 1314 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ 1315 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ 1316 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ 1317 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ 1318 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ 1319 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ 1320 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ 1321 1322 /******************* Bit definition for CAN_TSR register ********************/ 1323 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ 1324 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ 1325 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ 1326 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ 1327 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ 1328 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ 1329 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ 1330 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ 1331 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ 1332 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ 1333 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ 1334 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ 1335 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ 1336 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ 1337 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ 1338 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ 1339 1340 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ 1341 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ 1342 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ 1343 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ 1344 1345 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ 1346 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ 1347 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ 1348 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ 1349 1350 /******************* Bit definition for CAN_RF0R register *******************/ 1351 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ 1352 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ 1353 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ 1354 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ 1355 1356 /******************* Bit definition for CAN_RF1R register *******************/ 1357 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ 1358 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ 1359 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ 1360 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ 1361 1362 /******************** Bit definition for CAN_IER register *******************/ 1363 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ 1364 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ 1365 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ 1366 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ 1367 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ 1368 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ 1369 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ 1370 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ 1371 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ 1372 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ 1373 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ 1374 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ 1375 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ 1376 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ 1377 1378 /******************** Bit definition for CAN_ESR register *******************/ 1379 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ 1380 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ 1381 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ 1382 1383 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ 1384 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ 1385 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ 1386 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ 1387 1388 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ 1389 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ 1390 1391 /******************* Bit definition for CAN_BTR register ********************/ 1392 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ 1393 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ 1394 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ 1395 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ 1396 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ 1397 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ 1398 1399 /*!<Mailbox registers */ 1400 /****************** Bit definition for CAN_TI0R register ********************/ 1401 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ 1402 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 1403 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 1404 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ 1405 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 1406 1407 /****************** Bit definition for CAN_TDT0R register *******************/ 1408 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 1409 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ 1410 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 1411 1412 /****************** Bit definition for CAN_TDL0R register *******************/ 1413 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 1414 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 1415 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 1416 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 1417 1418 /****************** Bit definition for CAN_TDH0R register *******************/ 1419 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 1420 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 1421 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 1422 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 1423 1424 /******************* Bit definition for CAN_TI1R register *******************/ 1425 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ 1426 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 1427 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 1428 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ 1429 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 1430 1431 /******************* Bit definition for CAN_TDT1R register ******************/ 1432 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 1433 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ 1434 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 1435 1436 /******************* Bit definition for CAN_TDL1R register ******************/ 1437 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 1438 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 1439 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 1440 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 1441 1442 /******************* Bit definition for CAN_TDH1R register ******************/ 1443 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 1444 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 1445 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 1446 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 1447 1448 /******************* Bit definition for CAN_TI2R register *******************/ 1449 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ 1450 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 1451 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 1452 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ 1453 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 1454 1455 /******************* Bit definition for CAN_TDT2R register ******************/ 1456 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 1457 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ 1458 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 1459 1460 /******************* Bit definition for CAN_TDL2R register ******************/ 1461 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 1462 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 1463 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 1464 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 1465 1466 /******************* Bit definition for CAN_TDH2R register ******************/ 1467 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 1468 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 1469 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 1470 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 1471 1472 /******************* Bit definition for CAN_RI0R register *******************/ 1473 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 1474 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 1475 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ 1476 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 1477 1478 /******************* Bit definition for CAN_RDT0R register ******************/ 1479 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 1480 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ 1481 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 1482 1483 /******************* Bit definition for CAN_RDL0R register ******************/ 1484 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 1485 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 1486 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 1487 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 1488 1489 /******************* Bit definition for CAN_RDH0R register ******************/ 1490 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 1491 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 1492 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 1493 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 1494 1495 /******************* Bit definition for CAN_RI1R register *******************/ 1496 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ 1497 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ 1498 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ 1499 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ 1500 1501 /******************* Bit definition for CAN_RDT1R register ******************/ 1502 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ 1503 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ 1504 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ 1505 1506 /******************* Bit definition for CAN_RDL1R register ******************/ 1507 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ 1508 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ 1509 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ 1510 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ 1511 1512 /******************* Bit definition for CAN_RDH1R register ******************/ 1513 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ 1514 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ 1515 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ 1516 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ 1517 1518 /*!<CAN filter registers */ 1519 /******************* Bit definition for CAN_FMR register ********************/ 1520 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ 1521 1522 /******************* Bit definition for CAN_FM1R register *******************/ 1523 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ 1524 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ 1525 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ 1526 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ 1527 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ 1528 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ 1529 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ 1530 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ 1531 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ 1532 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ 1533 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ 1534 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ 1535 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ 1536 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ 1537 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ 1538 1539 /******************* Bit definition for CAN_FS1R register *******************/ 1540 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ 1541 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ 1542 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ 1543 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ 1544 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ 1545 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ 1546 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ 1547 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ 1548 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ 1549 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ 1550 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ 1551 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ 1552 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ 1553 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ 1554 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ 1555 1556 /****************** Bit definition for CAN_FFA1R register *******************/ 1557 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ 1558 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ 1559 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ 1560 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ 1561 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ 1562 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ 1563 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ 1564 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ 1565 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ 1566 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ 1567 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ 1568 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ 1569 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ 1570 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ 1571 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ 1572 1573 /******************* Bit definition for CAN_FA1R register *******************/ 1574 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ 1575 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ 1576 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ 1577 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ 1578 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ 1579 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ 1580 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ 1581 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ 1582 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ 1583 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ 1584 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ 1585 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ 1586 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ 1587 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ 1588 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ 1589 1590 /******************* Bit definition for CAN_F0R1 register *******************/ 1591 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1592 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1593 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1594 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1595 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1596 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1597 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1598 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1599 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1600 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1601 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1602 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1603 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1604 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1605 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1606 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1607 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1608 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1609 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1610 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1611 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1612 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1613 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1614 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1615 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1616 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1617 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1618 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1619 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1620 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1621 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1622 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1623 1624 /******************* Bit definition for CAN_F1R1 register *******************/ 1625 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1626 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1627 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1628 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1629 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1630 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1631 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1632 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1633 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1634 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1635 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1636 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1637 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1638 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1639 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1640 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1641 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1642 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1643 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1644 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1645 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1646 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1647 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1648 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1649 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1650 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1651 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1652 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1653 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1654 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1655 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1656 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1657 1658 /******************* Bit definition for CAN_F2R1 register *******************/ 1659 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1660 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1661 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1662 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1663 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1664 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1665 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1666 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1667 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1668 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1669 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1670 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1671 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1672 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1673 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1674 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1675 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1676 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1677 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1678 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1679 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1680 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1681 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1682 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1683 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1684 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1685 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1686 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1687 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1688 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1689 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1690 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1691 1692 /******************* Bit definition for CAN_F3R1 register *******************/ 1693 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1694 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1695 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1696 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1697 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1698 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1699 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1700 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1701 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1702 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1703 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1704 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1705 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1706 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1707 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1708 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1709 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1710 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1711 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1712 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1713 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1714 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1715 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1716 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1717 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1718 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1719 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1720 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1721 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1722 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1723 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1724 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1725 1726 /******************* Bit definition for CAN_F4R1 register *******************/ 1727 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1728 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1729 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1730 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1731 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1732 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1733 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1734 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1735 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1736 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1737 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1738 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1739 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1740 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1741 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1742 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1743 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1744 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1745 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1746 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1747 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1748 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1749 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1750 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1751 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1752 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1753 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1754 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1755 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1756 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1757 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1758 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1759 1760 /******************* Bit definition for CAN_F5R1 register *******************/ 1761 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1762 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1763 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1764 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1765 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1766 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1767 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1768 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1769 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1770 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1771 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1772 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1773 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1774 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1775 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1776 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1777 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1778 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1779 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1780 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1781 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1782 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1783 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1784 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1785 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1786 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1787 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1788 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1789 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1790 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1791 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1792 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1793 1794 /******************* Bit definition for CAN_F6R1 register *******************/ 1795 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1796 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1797 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1798 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1799 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1800 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1801 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1802 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1803 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1804 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1805 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1806 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1807 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1808 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1809 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1810 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1811 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1812 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1813 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1814 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1815 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1816 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1817 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1818 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1819 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1820 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1821 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1822 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1823 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1824 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1825 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1826 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1827 1828 /******************* Bit definition for CAN_F7R1 register *******************/ 1829 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1830 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1831 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1832 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1833 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1834 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1835 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1836 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1837 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1838 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1839 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1840 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1841 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1842 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1843 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1844 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1845 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1846 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1847 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1848 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1849 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1850 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1851 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1852 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1853 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1854 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1855 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1856 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1857 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1858 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1859 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1860 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1861 1862 /******************* Bit definition for CAN_F8R1 register *******************/ 1863 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1864 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1865 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1866 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1867 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1868 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1869 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1870 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1871 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1872 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1873 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1874 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1875 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1876 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1877 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1878 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1879 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1880 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1881 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1882 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1883 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1884 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1885 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1886 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1887 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1888 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1889 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1890 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1891 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1892 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1893 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1894 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1895 1896 /******************* Bit definition for CAN_F9R1 register *******************/ 1897 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1898 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1899 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1900 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1901 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1902 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1903 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1904 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1905 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1906 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1907 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1908 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1909 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1910 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1911 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1912 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1913 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1914 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1915 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1916 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1917 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1918 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1919 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1920 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1921 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1922 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1923 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1924 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1925 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1926 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1927 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1928 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1929 1930 /******************* Bit definition for CAN_F10R1 register ******************/ 1931 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1932 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1933 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1934 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1935 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1936 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1937 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1938 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1939 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1940 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1941 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1942 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1943 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1944 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1945 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1946 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1947 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1948 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1949 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1950 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1951 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1952 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1953 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1954 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1955 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1956 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1957 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1958 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1959 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1960 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1961 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1962 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1963 1964 /******************* Bit definition for CAN_F11R1 register ******************/ 1965 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 1966 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 1967 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 1968 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 1969 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 1970 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 1971 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 1972 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 1973 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 1974 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 1975 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 1976 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 1977 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 1978 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 1979 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 1980 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 1981 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 1982 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 1983 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 1984 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 1985 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 1986 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 1987 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 1988 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 1989 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 1990 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 1991 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 1992 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 1993 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 1994 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 1995 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 1996 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 1997 1998 /******************* Bit definition for CAN_F12R1 register ******************/ 1999 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2000 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2001 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2002 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2003 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2004 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2005 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2006 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2007 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2008 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2009 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2010 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2011 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2012 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2013 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2014 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2015 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2016 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2017 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2018 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2019 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2020 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2021 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2022 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2023 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2024 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2025 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2026 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2027 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2028 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2029 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2030 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2031 2032 /******************* Bit definition for CAN_F13R1 register ******************/ 2033 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2034 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2035 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2036 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2037 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2038 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2039 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2040 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2041 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2042 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2043 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2044 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2045 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2046 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2047 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2048 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2049 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2050 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2051 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2052 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2053 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2054 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2055 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2056 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2057 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2058 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2059 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2060 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2061 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2062 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2063 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2064 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2065 2066 /******************* Bit definition for CAN_F0R2 register *******************/ 2067 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2068 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2069 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2070 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2071 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2072 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2073 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2074 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2075 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2076 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2077 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2078 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2079 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2080 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2081 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2082 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2083 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2084 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2085 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2086 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2087 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2088 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2089 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2090 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2091 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2092 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2093 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2094 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2095 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2096 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2097 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2098 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2099 2100 /******************* Bit definition for CAN_F1R2 register *******************/ 2101 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2102 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2103 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2104 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2105 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2106 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2107 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2108 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2109 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2110 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2111 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2112 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2113 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2114 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2115 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2116 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2117 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2118 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2119 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2120 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2121 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2122 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2123 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2124 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2125 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2126 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2127 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2128 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2129 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2130 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2131 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2132 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2133 2134 /******************* Bit definition for CAN_F2R2 register *******************/ 2135 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2136 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2137 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2138 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2139 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2140 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2141 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2142 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2143 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2144 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2145 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2146 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2147 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2148 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2149 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2150 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2151 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2152 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2153 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2154 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2155 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2156 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2157 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2158 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2159 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2160 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2161 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2162 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2163 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2164 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2165 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2166 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2167 2168 /******************* Bit definition for CAN_F3R2 register *******************/ 2169 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2170 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2171 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2172 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2173 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2174 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2175 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2176 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2177 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2178 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2179 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2180 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2181 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2182 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2183 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2184 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2185 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2186 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2187 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2188 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2189 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2190 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2191 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2192 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2193 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2194 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2195 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2196 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2197 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2198 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2199 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2200 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2201 2202 /******************* Bit definition for CAN_F4R2 register *******************/ 2203 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2204 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2205 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2206 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2207 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2208 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2209 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2210 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2211 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2212 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2213 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2214 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2215 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2216 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2217 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2218 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2219 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2220 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2221 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2222 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2223 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2224 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2225 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2226 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2227 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2228 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2229 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2230 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2231 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2232 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2233 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2234 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2235 2236 /******************* Bit definition for CAN_F5R2 register *******************/ 2237 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2238 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2239 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2240 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2241 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2242 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2243 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2244 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2245 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2246 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2247 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2248 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2249 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2250 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2251 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2252 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2253 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2254 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2255 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2256 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2257 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2258 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2259 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2260 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2261 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2262 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2263 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2264 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2265 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2266 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2267 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2268 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2269 2270 /******************* Bit definition for CAN_F6R2 register *******************/ 2271 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2272 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2273 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2274 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2275 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2276 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2277 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2278 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2279 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2280 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2281 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2282 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2283 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2284 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2285 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2286 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2287 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2288 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2289 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2290 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2291 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2292 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2293 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2294 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2295 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2296 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2297 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2298 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2299 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2300 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2301 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2302 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2303 2304 /******************* Bit definition for CAN_F7R2 register *******************/ 2305 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2306 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2307 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2308 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2309 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2310 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2311 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2312 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2313 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2314 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2315 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2316 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2317 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2318 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2319 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2320 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2321 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2322 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2323 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2324 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2325 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2326 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2327 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2328 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2329 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2330 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2331 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2332 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2333 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2334 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2335 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2336 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2337 2338 /******************* Bit definition for CAN_F8R2 register *******************/ 2339 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2340 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2341 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2342 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2343 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2344 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2345 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2346 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2347 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2348 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2349 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2350 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2351 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2352 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2353 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2354 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2355 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2356 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2357 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2358 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2359 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2360 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2361 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2362 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2363 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2364 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2365 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2366 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2367 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2368 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2369 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2370 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2371 2372 /******************* Bit definition for CAN_F9R2 register *******************/ 2373 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2374 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2375 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2376 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2377 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2378 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2379 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2380 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2381 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2382 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2383 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2384 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2385 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2386 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2387 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2388 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2389 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2390 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2391 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2392 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2393 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2394 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2395 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2396 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2397 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2398 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2399 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2400 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2401 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2402 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2403 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2404 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2405 2406 /******************* Bit definition for CAN_F10R2 register ******************/ 2407 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2408 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2409 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2410 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2411 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2412 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2413 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2414 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2415 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2416 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2417 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2418 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2419 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2420 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2421 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2422 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2423 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2424 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2425 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2426 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2427 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2428 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2429 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2430 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2431 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2432 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2433 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2434 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2435 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2436 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2437 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2438 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2439 2440 /******************* Bit definition for CAN_F11R2 register ******************/ 2441 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2442 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2443 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2444 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2445 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2446 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2447 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2448 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2449 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2450 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2451 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2452 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2453 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2454 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2455 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2456 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2457 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2458 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2459 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2460 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2461 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2462 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2463 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2464 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2465 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2466 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2467 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2468 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2469 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2470 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2471 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2472 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2473 2474 /******************* Bit definition for CAN_F12R2 register ******************/ 2475 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2476 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2477 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2478 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2479 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2480 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2481 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2482 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2483 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2484 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2485 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2486 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2487 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2488 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2489 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2490 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2491 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2492 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2493 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2494 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2495 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2496 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2497 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2498 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2499 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2500 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2501 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2502 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2503 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2504 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2505 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2506 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2507 2508 /******************* Bit definition for CAN_F13R2 register ******************/ 2509 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ 2510 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ 2511 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ 2512 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ 2513 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ 2514 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ 2515 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ 2516 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ 2517 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ 2518 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ 2519 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ 2520 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ 2521 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ 2522 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ 2523 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ 2524 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ 2525 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ 2526 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ 2527 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ 2528 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ 2529 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ 2530 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ 2531 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ 2532 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ 2533 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ 2534 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ 2535 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ 2536 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ 2537 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ 2538 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ 2539 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ 2540 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ 2541 2542 2543 /******************************************************************************/ 2544 /* */ 2545 /* HDMI-CEC (CEC) */ 2546 /* */ 2547 /******************************************************************************/ 2548 2549 /******************* Bit definition for CEC_CR register *********************/ 2550 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */ 2551 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */ 2552 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */ 2553 2554 /******************* Bit definition for CEC_CFGR register *******************/ 2555 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */ 2556 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */ 2557 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */ 2558 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */ 2559 #define CEC_CFGR_LREGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */ 2560 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */ 2561 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */ 2562 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */ 2563 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */ 2564 2565 /******************* Bit definition for CEC_TXDR register *******************/ 2566 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */ 2567 2568 /******************* Bit definition for CEC_RXDR register *******************/ 2569 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */ 2570 2571 /******************* Bit definition for CEC_ISR register ********************/ 2572 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */ 2573 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */ 2574 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */ 2575 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */ 2576 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */ 2577 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */ 2578 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */ 2579 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */ 2580 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */ 2581 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */ 2582 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */ 2583 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */ 2584 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */ 2585 2586 /******************* Bit definition for CEC_IER register ********************/ 2587 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */ 2588 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */ 2589 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */ 2590 #define CEC_IER_BREIEIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */ 2591 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/ 2592 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */ 2593 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */ 2594 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */ 2595 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */ 2596 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */ 2597 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */ 2598 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */ 2599 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */ 2600 2601 /******************************************************************************/ 2602 /* */ 2603 /* Analog Comparators (COMP) */ 2604 /* */ 2605 /******************************************************************************/ 2606 /*********************** Bit definition for COMP_CSR register ***************/ 2607 /* COMP1 bits definition */ 2608 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */ 2609 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */ 2610 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */ 2611 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */ 2612 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */ 2613 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */ 2614 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */ 2615 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */ 2616 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */ 2617 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */ 2618 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */ 2619 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */ 2620 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */ 2621 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */ 2622 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */ 2623 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */ 2624 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */ 2625 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */ 2626 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */ 2627 /* COMP2 bits definition */ 2628 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */ 2629 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */ 2630 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */ 2631 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */ 2632 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */ 2633 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */ 2634 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */ 2635 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */ 2636 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */ 2637 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */ 2638 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */ 2639 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */ 2640 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */ 2641 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */ 2642 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */ 2643 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */ 2644 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */ 2645 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ 2646 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ 2647 2648 /******************************************************************************/ 2649 /* */ 2650 /* CRC calculation unit (CRC) */ 2651 /* */ 2652 /******************************************************************************/ 2653 /******************* Bit definition for CRC_DR register *********************/ 2654 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ 2655 2656 /******************* Bit definition for CRC_IDR register ********************/ 2657 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ 2658 2659 /******************** Bit definition for CRC_CR register ********************/ 2660 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ 2661 #define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits (only for STM32F072 devices)*/ 2662 #define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for STM32F072 devices) */ 2663 #define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for STM32F072 devices) */ 2664 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */ 2665 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */ 2666 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */ 2667 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */ 2668 2669 /******************* Bit definition for CRC_INIT register *******************/ 2670 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ 2671 2672 /******************* Bit definition for CRC_POL register ********************/ 2673 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for STM32F072 devices) */ 2674 2675 /******************************************************************************/ 2676 /* */ 2677 /* CRS Clock Recovery System */ 2678 /* (Available only for STM32F072 devices) */ 2679 /******************************************************************************/ 2680 2681 /******************* Bit definition for CRS_CR register *********************/ 2682 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */ 2683 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */ 2684 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */ 2685 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/ 2686 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */ 2687 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */ 2688 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */ 2689 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */ 2690 2691 /******************* Bit definition for CRS_CFGR register *********************/ 2692 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */ 2693 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */ 2694 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */ 2695 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */ 2696 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */ 2697 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */ 2698 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */ 2699 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */ 2700 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */ 2701 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */ 2702 2703 /******************* Bit definition for CRS_ISR register *********************/ 2704 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */ 2705 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */ 2706 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */ 2707 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */ 2708 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */ 2709 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */ 2710 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */ 2711 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */ 2712 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */ 2713 2714 /******************* Bit definition for CRS_ICR register *********************/ 2715 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */ 2716 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */ 2717 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */ 2718 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */ 2719 2720 /******************************************************************************/ 2721 /* */ 2722 /* Digital to Analog Converter (DAC) */ 2723 /* */ 2724 /******************************************************************************/ 2725 /******************** Bit definition for DAC_CR register ********************/ 2726 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ 2727 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ 2728 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ 2729 2730 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ 2731 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ 2732 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ 2733 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ 2734 2735 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) */ 2736 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ 2737 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ 2738 2739 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) */ 2740 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 2741 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 2742 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ 2743 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ 2744 2745 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ 2746 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Underrun Interrupt enable */ 2747 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ 2748 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ 2749 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ 2750 2751 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ 2752 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ 2753 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ 2754 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ 2755 2756 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ 2757 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ 2758 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ 2759 2760 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ 2761 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ 2762 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ 2763 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ 2764 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ 2765 2766 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ 2767 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA Underrun Interrupt enable */ 2768 2769 /***************** Bit definition for DAC_SWTRIGR register ******************/ 2770 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */ 2771 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */ 2772 2773 /***************** Bit definition for DAC_DHR12R1 register ******************/ 2774 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ 2775 2776 /***************** Bit definition for DAC_DHR12L1 register ******************/ 2777 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ 2778 2779 /****************** Bit definition for DAC_DHR8R1 register ******************/ 2780 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */ 2781 2782 /******************* Bit definition for DAC_DOR1 register *******************/ 2783 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */ 2784 2785 /******************** Bit definition for DAC_SR register ********************/ 2786 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ 2787 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) */ 2788 2789 /******************************************************************************/ 2790 /* */ 2791 /* Debug MCU (DBGMCU) */ 2792 /* */ 2793 /******************************************************************************/ 2794 2795 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 2796 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */ 2797 2798 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */ 2799 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */ 2800 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */ 2801 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */ 2802 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */ 2803 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */ 2804 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */ 2805 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */ 2806 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */ 2807 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */ 2808 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */ 2809 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */ 2810 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */ 2811 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */ 2812 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */ 2813 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */ 2814 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */ 2815 2816 /****************** Bit definition for DBGMCU_CR register *******************/ 2817 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */ 2818 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */ 2819 2820 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 2821 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */ 2822 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */ 2823 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/ 2824 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted (only for STM32F072 devices) */ 2825 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */ 2826 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */ 2827 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */ 2828 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */ 2829 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 2830 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted (only for STM32F072 devices) */ 2831 2832 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 2833 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */ 2834 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */ 2835 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */ 2836 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */ 2837 2838 /******************************************************************************/ 2839 /* */ 2840 /* DMA Controller (DMA) */ 2841 /* */ 2842 /******************************************************************************/ 2843 2844 /******************* Bit definition for DMA_ISR register ********************/ 2845 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ 2846 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ 2847 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ 2848 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ 2849 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ 2850 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ 2851 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ 2852 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ 2853 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ 2854 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ 2855 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ 2856 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ 2857 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ 2858 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ 2859 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ 2860 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ 2861 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ 2862 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ 2863 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ 2864 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ 2865 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag (only for STM32F072 devices) */ 2866 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag (only for STM32F072 devices) */ 2867 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag (only for STM32F072 devices) */ 2868 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag (only for STM32F072 devices) */ 2869 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag (only for STM32F072 devices) */ 2870 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag (only for STM32F072 devices) */ 2871 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag (only for STM32F072 devices) */ 2872 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag (only for STM32F072 devices) */ 2873 2874 /******************* Bit definition for DMA_IFCR register *******************/ 2875 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ 2876 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ 2877 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ 2878 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ 2879 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ 2880 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ 2881 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ 2882 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ 2883 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ 2884 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ 2885 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ 2886 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ 2887 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ 2888 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ 2889 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ 2890 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ 2891 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ 2892 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ 2893 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ 2894 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ 2895 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear (only for STM32F072 devices) */ 2896 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear (only for STM32F072 devices) */ 2897 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear (only for STM32F072 devices) */ 2898 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear (only for STM32F072 devices) */ 2899 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear (only for STM32F072 devices) */ 2900 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear (only for STM32F072 devices) */ 2901 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear (only for STM32F072 devices) */ 2902 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear (only for STM32F072 devices) */ 2903 2904 /******************* Bit definition for DMA_CCR register ********************/ 2905 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ 2906 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ 2907 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ 2908 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ 2909 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ 2910 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ 2911 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ 2912 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ 2913 2914 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ 2915 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 2916 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 2917 2918 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ 2919 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 2920 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 2921 2922 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/ 2923 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 2924 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 2925 2926 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ 2927 2928 /****************** Bit definition for DMA_CNDTR register *******************/ 2929 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ 2930 2931 /****************** Bit definition for DMA_CPAR register ********************/ 2932 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ 2933 2934 /****************** Bit definition for DMA_CMAR register ********************/ 2935 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ 2936 2937 /****************** Bit definition for DMA_RMPCR1 register ********************/ 2938 #define DMA_RMPCR1_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA1 */ 2939 #define DMA_RMPCR1_CH1_ADC ((uint32_t)0x00000001) /*!< Remap ADC on DMA1 Channel 1*/ 2940 #define DMA_RMPCR1_CH1_TIM17_CH1 ((uint32_t)0x00000007) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */ 2941 #define DMA_RMPCR1_CH1_TIM17_UP ((uint32_t)0x00000007) /*!< Remap TIM17 up on DMA1 channel 1 */ 2942 #define DMA_RMPCR1_CH1_USART1_RX ((uint32_t)0x00000008) /*!< Remap USART1 Rx on DMA1 channel 1 */ 2943 #define DMA_RMPCR1_CH1_USART2_RX ((uint32_t)0x00000009) /*!< Remap USART2 Rx on DMA1 channel 1 */ 2944 #define DMA_RMPCR1_CH1_USART3_RX ((uint32_t)0x0000000A) /*!< Remap USART3 Rx on DMA1 channel 1 */ 2945 #define DMA_RMPCR1_CH1_USART4_RX ((uint32_t)0x0000000B) /*!< Remap USART4 Rx on DMA1 channel 1 */ 2946 #define DMA_RMPCR1_CH1_USART5_RX ((uint32_t)0x0000000C) /*!< Remap USART5 Rx on DMA1 channel 1 */ 2947 #define DMA_RMPCR1_CH1_USART6_RX ((uint32_t)0x0000000D) /*!< Remap USART6 Rx on DMA1 channel 1 */ 2948 #define DMA_RMPCR1_CH1_USART7_RX ((uint32_t)0x0000000E) /*!< Remap USART7 Rx on DMA1 channel 1 */ 2949 #define DMA_RMPCR1_CH1_USART8_RX ((uint32_t)0x0000000F) /*!< Remap USART8 Rx on DMA1 channel 1 */ 2950 #define DMA_RMPCR1_CH2_ADC ((uint32_t)0x00000010) /*!< Remap ADC on DMA1 channel 2 */ 2951 #define DMA_RMPCR1_CH2_I2C1_TX ((uint32_t)0x00000020) /*!< Remap I2C1 Tx on DMA1 channel 2 */ 2952 #define DMA_RMPCR1_CH2_SPI_1RX ((uint32_t)0x00000030) /*!< Remap SPI1 Rx on DMA1 channel 2 */ 2953 #define DMA_RMPCR1_CH2_TIM1_CH1 ((uint32_t)0x00000040) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */ 2954 #define DMA_RMPCR1_CH2_TIM17_CH1 ((uint32_t)0x00000070) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */ 2955 #define DMA_RMPCR1_CH2_TIM17_UP ((uint32_t)0x00000070) /*!< Remap TIM17 up on DMA1 channel 2 */ 2956 #define DMA_RMPCR1_CH2_USART1_TX ((uint32_t)0x00000080) /*!< Remap USART1 Tx on DMA1 channel 2 */ 2957 #define DMA_RMPCR1_CH2_USART2_TX ((uint32_t)0x00000090) /*!< Remap USART2 Tx on DMA1 channel 2 */ 2958 #define DMA_RMPCR1_CH2_USART3_TX ((uint32_t)0x000000A0) /*!< Remap USART3 Tx on DMA1 channel 2 */ 2959 #define DMA_RMPCR1_CH2_USART4_TX ((uint32_t)0x000000B0) /*!< Remap USART4 Tx on DMA1 channel 2 */ 2960 #define DMA_RMPCR1_CH2_USART5_TX ((uint32_t)0x000000C0) /*!< Remap USART5 Tx on DMA1 channel 2 */ 2961 #define DMA_RMPCR1_CH2_USART6_TX ((uint32_t)0x000000D0) /*!< Remap USART6 Tx on DMA1 channel 2 */ 2962 #define DMA_RMPCR1_CH2_USART7_TX ((uint32_t)0x000000E0) /*!< Remap USART7 Tx on DMA1 channel 2 */ 2963 #define DMA_RMPCR1_CH2_USART8_TX ((uint32_t)0x000000F0) /*!< Remap USART8 Tx on DMA1 channel 2 */ 2964 #define DMA_RMPCR1_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA1 channel 3 */ 2965 #define DMA_RMPCR1_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC Channel 1on DMA1 channel 3 */ 2966 #define DMA_RMPCR1_CH3_I2C1_RX ((uint32_t)0x00000200) /*!< Remap I2C1 Rx on DMA1 channel 3 */ 2967 #define DMA_RMPCR1_CH3_SPI1_TX ((uint32_t)0x00000300) /*!< Remap SPI1 Tx on DMA1 channel 3 */ 2968 #define DMA_RMPCR1_CH3_TIM1_CH2 ((uint32_t)0x00000400) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */ 2969 #define DMA_RMPCR1_CH3_TIM2_CH2 ((uint32_t)0x00000500) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */ 2970 #define DMA_RMPCR1_CH3_TIM16_CH1 ((uint32_t)0x00000700) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */ 2971 #define DMA_RMPCR1_CH3_TIM16_UP ((uint32_t)0x00000700) /*!< Remap TIM16 up on DMA1 channel 3 */ 2972 #define DMA_RMPCR1_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA1 channel 3 */ 2973 #define DMA_RMPCR1_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA1 channel 3 */ 2974 #define DMA_RMPCR1_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA1 channel 3 */ 2975 #define DMA_RMPCR1_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA1 channel 3 */ 2976 #define DMA_RMPCR1_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA1 channel 3 */ 2977 #define DMA_RMPCR1_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA1 channel 3 */ 2978 #define DMA_RMPCR1_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA1 channel 3 */ 2979 #define DMA_RMPCR1_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA1 channel 3 */ 2980 #define DMA_RMPCR1_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA1 channel 4 */ 2981 #define DMA_RMPCR1_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC Channel 2 on DMA1 channel 4 */ 2982 #define DMA_RMPCR1_CH4_I2C2_TX ((uint32_t)0x00002000) /*!< Remap I2C2 Tx on DMA1 channel 4 */ 2983 #define DMA_RMPCR1_CH4_SPI2_RX ((uint32_t)0x00003000) /*!< Remap SPI2 Rx on DMA1 channel 4 */ 2984 #define DMA_RMPCR1_CH4_TIM2_CH4 ((uint32_t)0x00005000) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */ 2985 #define DMA_RMPCR1_CH4_TIM3_CH1 ((uint32_t)0x00006000) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */ 2986 #define DMA_RMPCR1_CH4_TIM3_TRIG ((uint32_t)0x00006000) /*!< Remap TIM3 Trig on DMA1 channel 4 */ 2987 #define DMA_RMPCR1_CH4_TIM16_CH1 ((uint32_t)0x00007000) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */ 2988 #define DMA_RMPCR1_CH4_TIM16_UP ((uint32_t)0x00007000) /*!< Remap TIM16 up on DMA1 channel 4 */ 2989 #define DMA_RMPCR1_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA1 channel 4 */ 2990 #define DMA_RMPCR1_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA1 channel 4 */ 2991 #define DMA_RMPCR1_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA1 channel 4 */ 2992 #define DMA_RMPCR1_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA1 channel 4 */ 2993 #define DMA_RMPCR1_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA1 channel 4 */ 2994 #define DMA_RMPCR1_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA1 channel 4 */ 2995 #define DMA_RMPCR1_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA1 channel 4 */ 2996 #define DMA_RMPCR1_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA1 channel 4 */ 2997 #define DMA_RMPCR1_CH5_I2C2_RX ((uint32_t)0x00020000) /*!< Remap I2C2 Rx on DMA1 channel 5 */ 2998 #define DMA_RMPCR1_CH5_SPI2_TX ((uint32_t)0x00030000) /*!< Remap SPI1 Tx on DMA1 channel 5 */ 2999 #define DMA_RMPCR1_CH5_TIM1_CH3 ((uint32_t)0x00040000) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */ 3000 #define DMA_RMPCR1_CH5_USART1_RX ((uint32_t)0x00080000) /*!< Remap USART1 Rx on DMA1 channel 5 */ 3001 #define DMA_RMPCR1_CH5_USART2_RX ((uint32_t)0x00090000) /*!< Remap USART2 Rx on DMA1 channel 5 */ 3002 #define DMA_RMPCR1_CH5_USART3_RX ((uint32_t)0x000A0000) /*!< Remap USART3 Rx on DMA1 channel 5 */ 3003 #define DMA_RMPCR1_CH5_USART4_RX ((uint32_t)0x000B0000) /*!< Remap USART4 Rx on DMA1 channel 5 */ 3004 #define DMA_RMPCR1_CH5_USART5_RX ((uint32_t)0x000C0000) /*!< Remap USART5 Rx on DMA1 channel 5 */ 3005 #define DMA_RMPCR1_CH5_USART6_RX ((uint32_t)0x000D0000) /*!< Remap USART6 Rx on DMA1 channel 5 */ 3006 #define DMA_RMPCR1_CH5_USART7_RX ((uint32_t)0x000E0000) /*!< Remap USART7 Rx on DMA1 channel 5 */ 3007 #define DMA_RMPCR1_CH5_USART8_RX ((uint32_t)0x000F0000) /*!< Remap USART8 Rx on DMA1 channel 5 */ 3008 #define DMA_RMPCR1_CH6_I2C1_TX ((uint32_t)0x00200000) /*!< Remap I2C1 Tx on DMA1 channel 6 */ 3009 #define DMA_RMPCR1_CH6_SPI2_RX ((uint32_t)0x00300000) /*!< Remap SPI2 Rx on DMA1 channel 6 */ 3010 #define DMA_RMPCR1_CH6_TIM1_CH1 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */ 3011 #define DMA_RMPCR1_CH6_TIM1_CH2 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */ 3012 #define DMA_RMPCR1_CH6_TIM1_CH3 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */ 3013 #define DMA_RMPCR1_CH6_TIM3_CH1 ((uint32_t)0x00600000) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */ 3014 #define DMA_RMPCR1_CH6_TIM3_TRIG ((uint32_t)0x00600000) /*!< Remap TIM3 Trig on DMA1 channel 6 */ 3015 #define DMA_RMPCR1_CH6_TIM16_CH1 ((uint32_t)0x00700000) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */ 3016 #define DMA_RMPCR1_CH6_TIM16_UP ((uint32_t)0x00700000) /*!< Remap TIM16 up on DMA1 channel 6 */ 3017 #define DMA_RMPCR1_CH6_USART1_RX ((uint32_t)0x00800000) /*!< Remap USART1 Rx on DMA1 channel 6 */ 3018 #define DMA_RMPCR1_CH6_USART2_RX ((uint32_t)0x00900000) /*!< Remap USART2 Rx on DMA1 channel 6 */ 3019 #define DMA_RMPCR1_CH6_USART3_RX ((uint32_t)0x00A00000) /*!< Remap USART3 Rx on DMA1 channel 6 */ 3020 #define DMA_RMPCR1_CH6_USART4_RX ((uint32_t)0x00B00000) /*!< Remap USART4 Rx on DMA1 channel 6 */ 3021 #define DMA_RMPCR1_CH6_USART5_RX ((uint32_t)0x00C00000) /*!< Remap USART5 Rx on DMA1 channel 6 */ 3022 #define DMA_RMPCR1_CH6_USART6_RX ((uint32_t)0x00D00000) /*!< Remap USART6 Rx on DMA1 channel 6 */ 3023 #define DMA_RMPCR1_CH6_USART7_RX ((uint32_t)0x00E00000) /*!< Remap USART7 Rx on DMA1 channel 6 */ 3024 #define DMA_RMPCR1_CH6_USART8_RX ((uint32_t)0x00F00000) /*!< Remap USART8 Rx on DMA1 channel 6 */ 3025 #define DMA_RMPCR1_CH7_I2C1_RX ((uint32_t)0x02000000) /*!< Remap I2C1 Rx on DMA1 channel 7 */ 3026 #define DMA_RMPCR1_CH7_SPI2_TX ((uint32_t)0x03000000) /*!< Remap SPI2 Tx on DMA1 channel 7 */ 3027 #define DMA_RMPCR1_CH7_TIM2_CH2 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */ 3028 #define DMA_RMPCR1_CH7_TIM2_CH4 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */ 3029 #define DMA_RMPCR1_CH7_TIM17_CH1 ((uint32_t)0x07000000) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */ 3030 #define DMA_RMPCR1_CH7_TIM17_UP ((uint32_t)0x07000000) /*!< Remap TIM17 up on DMA1 channel 7 */ 3031 #define DMA_RMPCR1_CH7_USART1_TX ((uint32_t)0x08000000) /*!< Remap USART1 Tx on DMA1 channel 7 */ 3032 #define DMA_RMPCR1_CH7_USART2_TX ((uint32_t)0x09000000) /*!< Remap USART2 Tx on DMA1 channel 7 */ 3033 #define DMA_RMPCR1_CH7_USART3_TX ((uint32_t)0x0A000000) /*!< Remap USART3 Tx on DMA1 channel 7 */ 3034 #define DMA_RMPCR1_CH7_USART4_TX ((uint32_t)0x0B000000) /*!< Remap USART4 Tx on DMA1 channel 7 */ 3035 #define DMA_RMPCR1_CH7_USART5_TX ((uint32_t)0x0C000000) /*!< Remap USART5 Tx on DMA1 channel 7 */ 3036 #define DMA_RMPCR1_CH7_USART6_TX ((uint32_t)0x0D000000) /*!< Remap USART6 Tx on DMA1 channel 7 */ 3037 #define DMA_RMPCR1_CH7_USART7_TX ((uint32_t)0x0E000000) /*!< Remap USART7 Tx on DMA1 channel 7 */ 3038 #define DMA_RMPCR1_CH7_USART8_TX ((uint32_t)0x0F000000) /*!< Remap USART8 Tx on DMA1 channel 7 */ 3039 3040 /****************** Bit definition for DMA_RMPCR2 register ********************/ 3041 #define DMA_RMPCR2_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA2 */ 3042 #define DMA_RMPCR2_CH1_I2C2_TX ((uint32_t)0x00000002) /*!< Remap I2C2 TX on DMA2 channel 1 */ 3043 #define DMA_RMPCR2_CH1_USART1_TX ((uint32_t)0x00000008) /*!< Remap USART1 Tx on DMA2 channel 1 */ 3044 #define DMA_RMPCR2_CH1_USART2_TX ((uint32_t)0x00000009) /*!< Remap USART2 Tx on DMA2 channel 1 */ 3045 #define DMA_RMPCR2_CH1_USART3_TX ((uint32_t)0x0000000A) /*!< Remap USART3 Tx on DMA2 channel 1 */ 3046 #define DMA_RMPCR2_CH1_USART4_TX ((uint32_t)0x0000000B) /*!< Remap USART4 Tx on DMA2 channel 1 */ 3047 #define DMA_RMPCR2_CH1_USART5_TX ((uint32_t)0x0000000C) /*!< Remap USART5 Tx on DMA2 channel 1 */ 3048 #define DMA_RMPCR2_CH1_USART6_TX ((uint32_t)0x0000000D) /*!< Remap USART6 Tx on DMA2 channel 1 */ 3049 #define DMA_RMPCR2_CH1_USART7_TX ((uint32_t)0x0000000E) /*!< Remap USART7 Tx on DMA2 channel 1 */ 3050 #define DMA_RMPCR2_CH1_USART8_TX ((uint32_t)0x0000000F) /*!< Remap USART8 Tx on DMA2 channel 1 */ 3051 #define DMA_RMPCR2_CH2_I2C2_RX ((uint32_t)0x00000020) /*!< Remap I2C2 Rx on DMA2 channel 2 */ 3052 #define DMA_RMPCR2_CH2_USART1_RX ((uint32_t)0x00000080) /*!< Remap USART1 Rx on DMA2 channel 2 */ 3053 #define DMA_RMPCR2_CH2_USART2_RX ((uint32_t)0x00000090) /*!< Remap USART2 Rx on DMA2 channel 2 */ 3054 #define DMA_RMPCR2_CH2_USART3_RX ((uint32_t)0x000000A0) /*!< Remap USART3 Rx on DMA2 channel 2 */ 3055 #define DMA_RMPCR2_CH2_USART4_RX ((uint32_t)0x000000B0) /*!< Remap USART4 Rx on DMA2 channel 2 */ 3056 #define DMA_RMPCR2_CH2_USART5_RX ((uint32_t)0x000000C0) /*!< Remap USART5 Rx on DMA2 channel 2 */ 3057 #define DMA_RMPCR2_CH2_USART6_RX ((uint32_t)0x000000D0) /*!< Remap USART6 Rx on DMA2 channel 2 */ 3058 #define DMA_RMPCR2_CH2_USART7_RX ((uint32_t)0x000000E0) /*!< Remap USART7 Rx on DMA2 channel 2 */ 3059 #define DMA_RMPCR2_CH2_USART8_RX ((uint32_t)0x000000F0) /*!< Remap USART8 Rx on DMA2 channel 2 */ 3060 #define DMA_RMPCR2_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA2 channel 3 */ 3061 #define DMA_RMPCR2_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC channel 1 on DMA2 channel 3 */ 3062 #define DMA_RMPCR2_CH3_SPI1_RX ((uint32_t)0x00000300) /*!< Remap SPI1 Rx on DMA2 channel 3 */ 3063 #define DMA_RMPCR2_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA2 channel 3 */ 3064 #define DMA_RMPCR2_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA2 channel 3 */ 3065 #define DMA_RMPCR2_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA2 channel 3 */ 3066 #define DMA_RMPCR2_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA2 channel 3 */ 3067 #define DMA_RMPCR2_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA2 channel 3 */ 3068 #define DMA_RMPCR2_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA2 channel 3 */ 3069 #define DMA_RMPCR2_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA2 channel 3 */ 3070 #define DMA_RMPCR2_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA2 channel 3 */ 3071 #define DMA_RMPCR2_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA2 channel 4 */ 3072 #define DMA_RMPCR2_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC channel 2 on DMA2 channel 4 */ 3073 #define DMA_RMPCR2_CH4_SPI1_TX ((uint32_t)0x00003000) /*!< Remap SPI1 Tx on DMA2 channel 4 */ 3074 #define DMA_RMPCR2_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA2 channel 4 */ 3075 #define DMA_RMPCR2_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA2 channel 4 */ 3076 #define DMA_RMPCR2_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA2 channel 4 */ 3077 #define DMA_RMPCR2_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA2 channel 4 */ 3078 #define DMA_RMPCR2_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA2 channel 4 */ 3079 #define DMA_RMPCR2_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA2 channel 4 */ 3080 #define DMA_RMPCR2_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA2 channel 4 */ 3081 #define DMA_RMPCR2_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA2 channel 4 */ 3082 #define DMA_RMPCR2_CH5_ADC ((uint32_t)0x00010000) /*!< Remap ADC on DMA2 channel 5 */ 3083 #define DMA_RMPCR2_CH5_USART1_TX ((uint32_t)0x00080000) /*!< Remap USART1 Tx on DMA2 channel 5 */ 3084 #define DMA_RMPCR2_CH5_USART2_TX ((uint32_t)0x00090000) /*!< Remap USART2 Tx on DMA2 channel 5 */ 3085 #define DMA_RMPCR2_CH5_USART3_TX ((uint32_t)0x000A0000) /*!< Remap USART3 Tx on DMA2 channel 5 */ 3086 #define DMA_RMPCR2_CH5_USART4_TX ((uint32_t)0x000B0000) /*!< Remap USART4 Tx on DMA2 channel 5 */ 3087 #define DMA_RMPCR2_CH5_USART5_TX ((uint32_t)0x000C0000) /*!< Remap USART5 Tx on DMA2 channel 5 */ 3088 #define DMA_RMPCR2_CH5_USART6_TX ((uint32_t)0x000D0000) /*!< Remap USART6 Tx on DMA2 channel 5 */ 3089 #define DMA_RMPCR2_CH5_USART7_TX ((uint32_t)0x000E0000) /*!< Remap USART7 Tx on DMA2 channel 5 */ 3090 #define DMA_RMPCR2_CH5_USART8_TX ((uint32_t)0x000F0000) /*!< Remap USART8 Tx on DMA2 channel 5 */ 3091 3092 /******************************************************************************/ 3093 /* */ 3094 /* External Interrupt/Event Controller (EXTI) */ 3095 /* */ 3096 /******************************************************************************/ 3097 /******************* Bit definition for EXTI_IMR register *******************/ 3098 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ 3099 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ 3100 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ 3101 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ 3102 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ 3103 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ 3104 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ 3105 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ 3106 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ 3107 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ 3108 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ 3109 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ 3110 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ 3111 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ 3112 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ 3113 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ 3114 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ 3115 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ 3116 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ 3117 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ 3118 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ 3119 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ 3120 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ 3121 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ 3122 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ 3123 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ 3124 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ 3125 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ 3126 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */ 3127 #define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */ 3128 #define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */ 3129 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */ 3130 3131 /****************** Bit definition for EXTI_EMR register ********************/ 3132 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ 3133 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ 3134 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ 3135 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ 3136 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ 3137 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ 3138 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ 3139 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ 3140 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ 3141 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ 3142 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ 3143 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ 3144 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ 3145 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ 3146 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ 3147 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ 3148 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ 3149 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ 3150 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ 3151 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ 3152 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ 3153 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ 3154 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ 3155 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ 3156 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ 3157 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ 3158 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ 3159 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ 3160 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */ 3161 #define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */ 3162 #define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */ 3163 #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */ 3164 3165 /******************* Bit definition for EXTI_RTSR register ******************/ 3166 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ 3167 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ 3168 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ 3169 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ 3170 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ 3171 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ 3172 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ 3173 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ 3174 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ 3175 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ 3176 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ 3177 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ 3178 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ 3179 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ 3180 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ 3181 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ 3182 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ 3183 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ 3184 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ 3185 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ 3186 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ 3187 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ 3188 3189 /******************* Bit definition for EXTI_FTSR register *******************/ 3190 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ 3191 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ 3192 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ 3193 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ 3194 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ 3195 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ 3196 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ 3197 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ 3198 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ 3199 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ 3200 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ 3201 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ 3202 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ 3203 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ 3204 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ 3205 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ 3206 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ 3207 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ 3208 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ 3209 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ 3210 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ 3211 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ 3212 3213 /******************* Bit definition for EXTI_SWIER register *******************/ 3214 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ 3215 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ 3216 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ 3217 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ 3218 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ 3219 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ 3220 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ 3221 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ 3222 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ 3223 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ 3224 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ 3225 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ 3226 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ 3227 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ 3228 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ 3229 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ 3230 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ 3231 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ 3232 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ 3233 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ 3234 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ 3235 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ 3236 3237 /****************** Bit definition for EXTI_PR register *********************/ 3238 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */ 3239 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */ 3240 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */ 3241 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */ 3242 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */ 3243 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */ 3244 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */ 3245 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */ 3246 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */ 3247 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */ 3248 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */ 3249 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */ 3250 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */ 3251 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */ 3252 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */ 3253 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */ 3254 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */ 3255 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */ 3256 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */ 3257 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */ 3258 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */ 3259 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */ 3260 3261 /******************************************************************************/ 3262 /* */ 3263 /* FLASH and Option Bytes Registers */ 3264 /* */ 3265 /******************************************************************************/ 3266 3267 /******************* Bit definition for FLASH_ACR register ******************/ 3268 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */ 3269 3270 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ 3271 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ 3272 3273 /****************** Bit definition for FLASH_KEYR register ******************/ 3274 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ 3275 3276 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 3277 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ 3278 3279 /****************** FLASH Keys **********************************************/ 3280 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */ 3281 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1 3282 to unlock the write access to the FPEC. */ 3283 3284 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */ 3285 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to 3286 unlock the write access to the option byte block */ 3287 3288 /****************** Bit definition for FLASH_SR register *******************/ 3289 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ 3290 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ 3291 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */ 3292 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ 3293 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */ 3294 3295 /******************* Bit definition for FLASH_CR register *******************/ 3296 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ 3297 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ 3298 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ 3299 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ 3300 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ 3301 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ 3302 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ 3303 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ 3304 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ 3305 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ 3306 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */ 3307 3308 /******************* Bit definition for FLASH_AR register *******************/ 3309 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ 3310 3311 /****************** Bit definition for FLASH_OBR register *******************/ 3312 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ 3313 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level bit 1 */ 3314 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level bit 2 */ 3315 3316 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */ 3317 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ 3318 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ 3319 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ 3320 #define FLASH_OBR_nBOOT0 ((uint32_t)0x00000800) /*!< nBOOT0 */ 3321 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ 3322 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */ 3323 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM Parity Check */ 3324 #define FLASH_OBR_nBOOT0_SW ((uint32_t)0x00008000) /*!< nBOOT0 SW (available only in the STM32F042 devices)*/ 3325 #define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< DATA0 */ 3326 #define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< DATA0 */ 3327 3328 /* Old BOOT1 bit definition, maintained for legacy purpose */ 3329 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1 3330 3331 /* Old OBR_VDDA bit definition, maintained for legacy purpose */ 3332 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR 3333 3334 /****************** Bit definition for FLASH_WRPR register ******************/ 3335 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ 3336 3337 /*----------------------------------------------------------------------------*/ 3338 3339 /****************** Bit definition for OB_RDP register **********************/ 3340 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ 3341 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ 3342 3343 /****************** Bit definition for OB_USER register *********************/ 3344 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ 3345 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ 3346 3347 /****************** Bit definition for OB_WRP0 register *********************/ 3348 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ 3349 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ 3350 3351 /****************** Bit definition for OB_WRP1 register *********************/ 3352 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ 3353 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ 3354 3355 /****************** Bit definition for OB_WRP2 register *********************/ 3356 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */ 3357 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */ 3358 3359 /****************** Bit definition for OB_WRP3 register *********************/ 3360 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */ 3361 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */ 3362 3363 /******************************************************************************/ 3364 /* */ 3365 /* General Purpose IOs (GPIO) */ 3366 /* */ 3367 /******************************************************************************/ 3368 /******************* Bit definition for GPIO_MODER register *****************/ 3369 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) 3370 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) 3371 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) 3372 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) 3373 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) 3374 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) 3375 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) 3376 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) 3377 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) 3378 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) 3379 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) 3380 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) 3381 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) 3382 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) 3383 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) 3384 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) 3385 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) 3386 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) 3387 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) 3388 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) 3389 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) 3390 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) 3391 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) 3392 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) 3393 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) 3394 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) 3395 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) 3396 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) 3397 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) 3398 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) 3399 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) 3400 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) 3401 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) 3402 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) 3403 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) 3404 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) 3405 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) 3406 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) 3407 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) 3408 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) 3409 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) 3410 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) 3411 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) 3412 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) 3413 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) 3414 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) 3415 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) 3416 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) 3417 3418 /****************** Bit definition for GPIO_OTYPER register *****************/ 3419 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) 3420 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) 3421 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) 3422 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) 3423 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) 3424 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) 3425 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) 3426 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) 3427 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) 3428 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) 3429 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) 3430 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) 3431 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) 3432 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) 3433 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) 3434 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) 3435 3436 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 3437 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003) 3438 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001) 3439 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002) 3440 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C) 3441 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004) 3442 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008) 3443 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030) 3444 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010) 3445 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020) 3446 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0) 3447 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040) 3448 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080) 3449 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300) 3450 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100) 3451 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200) 3452 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00) 3453 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400) 3454 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800) 3455 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000) 3456 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000) 3457 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000) 3458 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000) 3459 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000) 3460 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000) 3461 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000) 3462 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000) 3463 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000) 3464 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000) 3465 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000) 3466 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000) 3467 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000) 3468 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000) 3469 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000) 3470 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000) 3471 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000) 3472 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000) 3473 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000) 3474 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000) 3475 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000) 3476 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000) 3477 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000) 3478 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000) 3479 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000) 3480 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000) 3481 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000) 3482 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000) 3483 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000) 3484 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000) 3485 3486 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */ 3487 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0 3488 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0 3489 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1 3490 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1 3491 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0 3492 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1 3493 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2 3494 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0 3495 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1 3496 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3 3497 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0 3498 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1 3499 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4 3500 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0 3501 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1 3502 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5 3503 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0 3504 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1 3505 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6 3506 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0 3507 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1 3508 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7 3509 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0 3510 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1 3511 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8 3512 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0 3513 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1 3514 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9 3515 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0 3516 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1 3517 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10 3518 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0 3519 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1 3520 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11 3521 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0 3522 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1 3523 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12 3524 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0 3525 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1 3526 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13 3527 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0 3528 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1 3529 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14 3530 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0 3531 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1 3532 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15 3533 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0 3534 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1 3535 3536 /******************* Bit definition for GPIO_PUPDR register ******************/ 3537 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) 3538 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) 3539 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) 3540 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) 3541 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) 3542 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) 3543 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) 3544 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) 3545 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) 3546 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) 3547 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) 3548 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) 3549 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) 3550 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) 3551 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) 3552 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) 3553 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) 3554 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) 3555 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) 3556 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) 3557 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) 3558 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) 3559 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) 3560 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) 3561 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) 3562 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) 3563 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) 3564 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) 3565 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) 3566 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) 3567 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) 3568 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) 3569 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) 3570 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) 3571 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) 3572 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) 3573 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) 3574 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) 3575 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) 3576 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) 3577 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) 3578 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) 3579 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) 3580 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) 3581 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) 3582 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) 3583 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) 3584 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) 3585 3586 /******************* Bit definition for GPIO_IDR register *******************/ 3587 #define GPIO_IDR_0 ((uint32_t)0x00000001) 3588 #define GPIO_IDR_1 ((uint32_t)0x00000002) 3589 #define GPIO_IDR_2 ((uint32_t)0x00000004) 3590 #define GPIO_IDR_3 ((uint32_t)0x00000008) 3591 #define GPIO_IDR_4 ((uint32_t)0x00000010) 3592 #define GPIO_IDR_5 ((uint32_t)0x00000020) 3593 #define GPIO_IDR_6 ((uint32_t)0x00000040) 3594 #define GPIO_IDR_7 ((uint32_t)0x00000080) 3595 #define GPIO_IDR_8 ((uint32_t)0x00000100) 3596 #define GPIO_IDR_9 ((uint32_t)0x00000200) 3597 #define GPIO_IDR_10 ((uint32_t)0x00000400) 3598 #define GPIO_IDR_11 ((uint32_t)0x00000800) 3599 #define GPIO_IDR_12 ((uint32_t)0x00001000) 3600 #define GPIO_IDR_13 ((uint32_t)0x00002000) 3601 #define GPIO_IDR_14 ((uint32_t)0x00004000) 3602 #define GPIO_IDR_15 ((uint32_t)0x00008000) 3603 3604 /****************** Bit definition for GPIO_ODR register ********************/ 3605 #define GPIO_ODR_0 ((uint32_t)0x00000001) 3606 #define GPIO_ODR_1 ((uint32_t)0x00000002) 3607 #define GPIO_ODR_2 ((uint32_t)0x00000004) 3608 #define GPIO_ODR_3 ((uint32_t)0x00000008) 3609 #define GPIO_ODR_4 ((uint32_t)0x00000010) 3610 #define GPIO_ODR_5 ((uint32_t)0x00000020) 3611 #define GPIO_ODR_6 ((uint32_t)0x00000040) 3612 #define GPIO_ODR_7 ((uint32_t)0x00000080) 3613 #define GPIO_ODR_8 ((uint32_t)0x00000100) 3614 #define GPIO_ODR_9 ((uint32_t)0x00000200) 3615 #define GPIO_ODR_10 ((uint32_t)0x00000400) 3616 #define GPIO_ODR_11 ((uint32_t)0x00000800) 3617 #define GPIO_ODR_12 ((uint32_t)0x00001000) 3618 #define GPIO_ODR_13 ((uint32_t)0x00002000) 3619 #define GPIO_ODR_14 ((uint32_t)0x00004000) 3620 #define GPIO_ODR_15 ((uint32_t)0x00008000) 3621 3622 /****************** Bit definition for GPIO_BSRR register ********************/ 3623 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) 3624 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) 3625 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) 3626 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) 3627 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) 3628 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) 3629 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) 3630 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) 3631 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) 3632 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) 3633 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) 3634 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) 3635 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) 3636 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) 3637 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) 3638 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) 3639 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) 3640 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) 3641 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) 3642 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) 3643 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) 3644 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) 3645 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) 3646 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) 3647 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) 3648 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) 3649 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) 3650 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) 3651 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) 3652 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) 3653 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) 3654 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) 3655 3656 /****************** Bit definition for GPIO_LCKR register ********************/ 3657 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) 3658 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) 3659 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) 3660 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) 3661 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) 3662 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) 3663 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) 3664 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) 3665 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) 3666 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) 3667 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) 3668 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) 3669 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) 3670 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) 3671 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) 3672 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) 3673 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) 3674 3675 /****************** Bit definition for GPIO_AFRL register ********************/ 3676 #define GPIO_AFRL_AFR0 ((uint32_t)0x0000000F) 3677 #define GPIO_AFRL_AFR1 ((uint32_t)0x000000F0) 3678 #define GPIO_AFRL_AFR2 ((uint32_t)0x00000F00) 3679 #define GPIO_AFRL_AFR3 ((uint32_t)0x0000F000) 3680 #define GPIO_AFRL_AFR4 ((uint32_t)0x000F0000) 3681 #define GPIO_AFRL_AFR5 ((uint32_t)0x00F00000) 3682 #define GPIO_AFRL_AFR6 ((uint32_t)0x0F000000) 3683 #define GPIO_AFRL_AFR7 ((uint32_t)0xF0000000) 3684 3685 /****************** Bit definition for GPIO_AFRH register ********************/ 3686 #define GPIO_AFRH_AFR8 ((uint32_t)0x0000000F) 3687 #define GPIO_AFRH_AFR9 ((uint32_t)0x000000F0) 3688 #define GPIO_AFRH_AFR10 ((uint32_t)0x00000F00) 3689 #define GPIO_AFRH_AFR11 ((uint32_t)0x0000F000) 3690 #define GPIO_AFRH_AFR12 ((uint32_t)0x000F0000) 3691 #define GPIO_AFRH_AFR13 ((uint32_t)0x00F00000) 3692 #define GPIO_AFRH_AFR14 ((uint32_t)0x0F000000) 3693 #define GPIO_AFRH_AFR15 ((uint32_t)0xF0000000) 3694 3695 /* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/ 3696 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFR0 3697 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFR1 3698 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFR2 3699 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFR3 3700 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFR4 3701 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFR5 3702 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFR6 3703 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFR7 3704 3705 /* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/ 3706 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFR8 3707 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFR9 3708 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFR10 3709 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFR11 3710 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFR12 3711 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFR13 3712 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFR14 3713 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFR15 3714 3715 /****************** Bit definition for GPIO_BRR register *********************/ 3716 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001) 3717 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002) 3718 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004) 3719 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008) 3720 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010) 3721 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020) 3722 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040) 3723 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080) 3724 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100) 3725 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200) 3726 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400) 3727 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800) 3728 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000) 3729 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000) 3730 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000) 3731 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000) 3732 3733 /******************************************************************************/ 3734 /* */ 3735 /* Inter-integrated Circuit Interface (I2C) */ 3736 /* */ 3737 /******************************************************************************/ 3738 3739 /******************* Bit definition for I2C_CR1 register *******************/ 3740 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */ 3741 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */ 3742 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */ 3743 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */ 3744 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */ 3745 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ 3746 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ 3747 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ 3748 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ 3749 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ 3750 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ 3751 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ 3752 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */ 3753 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */ 3754 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */ 3755 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */ 3756 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */ 3757 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */ 3758 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */ 3759 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ 3760 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ 3761 3762 /****************** Bit definition for I2C_CR2 register ********************/ 3763 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ 3764 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ 3765 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */ 3766 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */ 3767 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */ 3768 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */ 3769 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */ 3770 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */ 3771 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */ 3772 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */ 3773 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */ 3774 3775 /******************* Bit definition for I2C_OAR1 register ******************/ 3776 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */ 3777 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */ 3778 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ 3779 3780 /******************* Bit definition for I2C_OAR2 register ******************/ 3781 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ 3782 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ 3783 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ 3784 3785 /******************* Bit definition for I2C_TIMINGR register *******************/ 3786 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ 3787 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */ 3788 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */ 3789 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */ 3790 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */ 3791 3792 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 3793 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */ 3794 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */ 3795 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */ 3796 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/ 3797 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */ 3798 3799 /****************** Bit definition for I2C_ISR register *********************/ 3800 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */ 3801 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */ 3802 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */ 3803 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/ 3804 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */ 3805 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */ 3806 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */ 3807 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */ 3808 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */ 3809 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */ 3810 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */ 3811 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */ 3812 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */ 3813 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */ 3814 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */ 3815 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */ 3816 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */ 3817 3818 /****************** Bit definition for I2C_ICR register *********************/ 3819 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */ 3820 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */ 3821 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */ 3822 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */ 3823 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */ 3824 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */ 3825 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */ 3826 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */ 3827 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */ 3828 3829 /****************** Bit definition for I2C_PECR register *********************/ 3830 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */ 3831 3832 /****************** Bit definition for I2C_RXDR register *********************/ 3833 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */ 3834 3835 /****************** Bit definition for I2C_TXDR register *********************/ 3836 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */ 3837 3838 /******************************************************************************/ 3839 /* */ 3840 /* Independent WATCHDOG (IWDG) */ 3841 /* */ 3842 /******************************************************************************/ 3843 /******************* Bit definition for IWDG_KR register ********************/ 3844 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ 3845 3846 /******************* Bit definition for IWDG_PR register ********************/ 3847 #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ 3848 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ 3849 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ 3850 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ 3851 3852 /******************* Bit definition for IWDG_RLR register *******************/ 3853 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ 3854 3855 /******************* Bit definition for IWDG_SR register ********************/ 3856 #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ 3857 #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ 3858 #define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */ 3859 3860 /******************* Bit definition for IWDG_KR register ********************/ 3861 #define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */ 3862 3863 /******************************************************************************/ 3864 /* */ 3865 /* Power Control (PWR) */ 3866 /* */ 3867 /******************************************************************************/ 3868 3869 /******************** Bit definition for PWR_CR register ********************/ 3870 #define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep */ 3871 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ 3872 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ 3873 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ 3874 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ 3875 3876 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ 3877 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ 3878 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ 3879 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ 3880 /* PVD level configuration */ 3881 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */ 3882 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */ 3883 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */ 3884 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */ 3885 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */ 3886 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */ 3887 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */ 3888 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */ 3889 3890 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ 3891 3892 /* Old Bit definition maintained for legacy purpose ****/ 3893 #define PWR_CR_LPSDSR PWR_CR_LPDS /*!< Low-power deepsleep */ 3894 3895 /******************* Bit definition for PWR_CSR register ********************/ 3896 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ 3897 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ 3898 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ 3899 #define PWR_CSR_VREFINTRDY ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready */ 3900 3901 #define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */ 3902 #define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */ 3903 #define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */ 3904 #define PWR_CSR_EWUP4 ((uint16_t)0x0800) /*!< Enable WKUP pin 4 */ 3905 #define PWR_CSR_EWUP5 ((uint16_t)0x1000) /*!< Enable WKUP pin 5 */ 3906 #define PWR_CSR_EWUP6 ((uint16_t)0x2000) /*!< Enable WKUP pin 6 */ 3907 #define PWR_CSR_EWUP7 ((uint16_t)0x4000) /*!< Enable WKUP pin 7 */ 3908 #define PWR_CSR_EWUP8 ((uint16_t)0x8000) /*!< Enable WKUP pin 8 */ 3909 3910 /* Old Bit definition maintained for legacy purpose ****/ 3911 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDY /*!< Internal voltage reference (VREFINT) ready flag */ 3912 /******************************************************************************/ 3913 /* */ 3914 /* Reset and Clock Control */ 3915 /* */ 3916 /******************************************************************************/ 3917 3918 /******************** Bit definition for RCC_CR register ********************/ 3919 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ 3920 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ 3921 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ 3922 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ 3923 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ 3924 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ 3925 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ 3926 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ 3927 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ 3928 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ 3929 3930 /******************* Bit definition for RCC_CFGR register *******************/ 3931 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ 3932 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 3933 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 3934 /* SW configuration */ 3935 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ 3936 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ 3937 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ 3938 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */ 3939 3940 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ 3941 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ 3942 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ 3943 /* SWS configuration */ 3944 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ 3945 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ 3946 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ 3947 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 used as system clock */ 3948 3949 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ 3950 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ 3951 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ 3952 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ 3953 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ 3954 /* HPRE configuration */ 3955 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ 3956 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ 3957 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ 3958 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ 3959 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ 3960 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ 3961 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ 3962 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ 3963 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ 3964 3965 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */ 3966 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 3967 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 3968 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */ 3969 /* PPRE configuration */ 3970 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ 3971 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ 3972 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ 3973 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ 3974 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ 3975 3976 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADC prescaler: Obsolete. Proper ADC clock selection is 3977 done inside the ADC_CFGR2 */ 3978 3979 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */ 3980 #define RCC_CFGR_PLLSRC_0 ((uint32_t)0x00008000) /*!< Bit 0 (available only in the STM32F072 devices) */ 3981 #define RCC_CFGR_PLLSRC_1 ((uint32_t)0x00010000) /*!< Bit 1 */ 3982 3983 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source; 3984 Old PREDIV1 bit definition, maintained for legacy purpose */ 3985 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ 3986 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI PREDIV clock selected as PLL entry clock source 3987 (This bit and configuration is only available for STM32F072 devices)*/ 3988 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE PREDIV clock selected as PLL entry clock source */ 3989 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48 PREDIV clock selected as PLL entry clock source */ 3990 3991 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ 3992 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ 3993 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ 3994 3995 /*!< Old bit definition maintained for legacy purposes */ 3996 #define RCC_CFGR_PLLSRC_HSI_Div2 RCC_CFGR_PLLSRC_HSI_DIV2 3997 3998 /* PLLMUL configuration */ 3999 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 4000 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ 4001 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ 4002 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ 4003 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ 4004 4005 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ 4006 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ 4007 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ 4008 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ 4009 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ 4010 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ 4011 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ 4012 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ 4013 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ 4014 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ 4015 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ 4016 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ 4017 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ 4018 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ 4019 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ 4020 4021 /* Old PLLMUL configuration bit definition maintained for legacy purposes */ 4022 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMUL /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 4023 #define RCC_CFGR_PLLMULL_0 RCC_CFGR_PLLMUL_0 /*!< Bit 0 */ 4024 #define RCC_CFGR_PLLMULL_1 RCC_CFGR_PLLMUL_1 /*!< Bit 1 */ 4025 #define RCC_CFGR_PLLMULL_2 RCC_CFGR_PLLMUL_2 /*!< Bit 2 */ 4026 #define RCC_CFGR_PLLMULL_3 RCC_CFGR_PLLMUL_3 /*!< Bit 3 */ 4027 4028 #define RCC_CFGR_PLLMULL2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */ 4029 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */ 4030 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */ 4031 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */ 4032 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */ 4033 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */ 4034 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */ 4035 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */ 4036 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMUL10 /*!< PLL input clock10 */ 4037 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */ 4038 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */ 4039 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */ 4040 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */ 4041 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */ 4042 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */ 4043 4044 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 4045 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ 4046 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ 4047 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ 4048 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ 4049 /* MCO configuration */ 4050 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ 4051 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */ 4052 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */ 4053 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */ 4054 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ 4055 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ 4056 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ 4057 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */ 4058 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */ 4059 4060 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (these bits are not available in the STM32F051 devices)*/ 4061 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)*/ 4062 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)*/ 4063 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)*/ 4064 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)*/ 4065 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)*/ 4066 #define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)*/ 4067 #define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)*/ 4068 #define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)*/ 4069 4070 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) */ 4071 4072 /******************* Bit definition for RCC_CIR register ********************/ 4073 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ 4074 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ 4075 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ 4076 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ 4077 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ 4078 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */ 4079 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */ 4080 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ 4081 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ 4082 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ 4083 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ 4084 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ 4085 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ 4086 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */ 4087 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */ 4088 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ 4089 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ 4090 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ 4091 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ 4092 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ 4093 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */ 4094 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */ 4095 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ 4096 4097 /***************** Bit definition for RCC_APB2RSTR register *****************/ 4098 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */ 4099 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */ 4100 #define RCC_APB2RSTR_USART8RST ((uint32_t)0x00000080) /*!< USART8 clock reset */ 4101 #define RCC_APB2RSTR_USART7RST ((uint32_t)0x00000040) /*!< USART7 clock reset */ 4102 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) /*!< USART6 clock reset */ 4103 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */ 4104 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */ 4105 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */ 4106 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */ 4107 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */ 4108 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */ 4109 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */ 4110 4111 /* Old ADC1 clock reset bit definition maintained for legacy purpose */ 4112 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST 4113 4114 /***************** Bit definition for RCC_APB1RSTR register *****************/ 4115 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */ 4116 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */ 4117 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */ 4118 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */ 4119 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */ 4120 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */ 4121 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */ 4122 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */ 4123 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */ 4124 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */ 4125 #define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000) /*!< USART 5 clock reset */ 4126 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */ 4127 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */ 4128 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */ 4129 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */ 4130 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */ 4131 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */ 4132 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */ 4133 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */ 4134 4135 /****************** Bit definition for RCC_AHBENR register ******************/ 4136 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */ 4137 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */ 4138 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ 4139 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ 4140 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ 4141 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */ 4142 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */ 4143 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */ 4144 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */ 4145 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */ 4146 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */ 4147 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */ 4148 4149 /* Old Bit definition maintained for legacy purpose */ 4150 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 4151 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */ 4152 4153 /***************** Bit definition for RCC_APB2ENR register ******************/ 4154 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */ 4155 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) /*!< USART6 clock enable */ 4156 #define RCC_APB2ENR_USART7EN ((uint32_t)0x00000040) /*!< USART7 clock enable */ 4157 #define RCC_APB2ENR_USART8EN ((uint32_t)0x00000080) /*!< USART8 clock enable */ 4158 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */ 4159 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */ 4160 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ 4161 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ 4162 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */ 4163 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */ 4164 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */ 4165 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */ 4166 4167 /* Old Bit definition maintained for legacy purpose */ 4168 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */ 4169 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 4170 4171 /***************** Bit definition for RCC_APB1ENR register ******************/ 4172 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */ 4173 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ 4174 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ 4175 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ 4176 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */ 4177 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ 4178 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */ 4179 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */ 4180 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */ 4181 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */ 4182 #define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000) /*!< USART5 clock enable */ 4183 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */ 4184 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */ 4185 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */ 4186 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */ 4187 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */ 4188 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */ 4189 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */ 4190 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */ 4191 4192 /******************* Bit definition for RCC_BDCR register *******************/ 4193 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ 4194 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ 4195 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ 4196 4197 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 4198 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */ 4199 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */ 4200 4201 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 4202 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ 4203 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ 4204 4205 /* RTC configuration */ 4206 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ 4207 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ 4208 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ 4209 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ 4210 4211 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ 4212 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ 4213 4214 /******************* Bit definition for RCC_CSR register ********************/ 4215 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ 4216 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ 4217 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */ 4218 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ 4219 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */ 4220 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ 4221 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ 4222 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ 4223 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ 4224 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ 4225 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ 4226 4227 /* Old Bit definition maintained for legacy purpose */ 4228 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 4229 /******************* Bit definition for RCC_AHBRSTR register ****************/ 4230 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */ 4231 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */ 4232 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */ 4233 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD clock reset */ 4234 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00020000) /*!< GPIOE clock reset */ 4235 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF clock reset */ 4236 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x00100000) /*!< TS clock reset */ 4237 4238 /* Old Bit definition maintained for legacy purpose */ 4239 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */ 4240 4241 /******************* Bit definition for RCC_CFGR2 register ******************/ 4242 /* PREDIV1 configuration */ 4243 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ 4244 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 4245 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 4246 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ 4247 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ 4248 4249 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ 4250 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ 4251 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ 4252 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ 4253 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ 4254 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ 4255 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ 4256 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ 4257 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ 4258 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ 4259 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ 4260 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ 4261 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ 4262 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ 4263 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ 4264 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ 4265 4266 /******************* Bit definition for RCC_CFGR3 register ******************/ 4267 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */ 4268 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ 4269 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ 4270 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ 4271 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */ 4272 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */ 4273 #define RCC_CFGR3_ADCSW ((uint32_t)0x00000100) /*!< ADCSW bits */ 4274 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ 4275 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ 4276 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ 4277 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */ 4278 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */ 4279 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */ 4280 4281 4282 /******************* Bit definition for RCC_CR2 register ********************/ 4283 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */ 4284 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */ 4285 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */ 4286 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */ 4287 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */ 4288 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */ 4289 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */ 4290 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */ 4291 4292 /******************************************************************************/ 4293 /* */ 4294 /* Real-Time Clock (RTC) */ 4295 /* */ 4296 /******************************************************************************/ 4297 /******************** Bits definition for RTC_TR register *******************/ 4298 #define RTC_TR_PM ((uint32_t)0x00400000) 4299 #define RTC_TR_HT ((uint32_t)0x00300000) 4300 #define RTC_TR_HT_0 ((uint32_t)0x00100000) 4301 #define RTC_TR_HT_1 ((uint32_t)0x00200000) 4302 #define RTC_TR_HU ((uint32_t)0x000F0000) 4303 #define RTC_TR_HU_0 ((uint32_t)0x00010000) 4304 #define RTC_TR_HU_1 ((uint32_t)0x00020000) 4305 #define RTC_TR_HU_2 ((uint32_t)0x00040000) 4306 #define RTC_TR_HU_3 ((uint32_t)0x00080000) 4307 #define RTC_TR_MNT ((uint32_t)0x00007000) 4308 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) 4309 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) 4310 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) 4311 #define RTC_TR_MNU ((uint32_t)0x00000F00) 4312 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) 4313 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) 4314 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) 4315 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) 4316 #define RTC_TR_ST ((uint32_t)0x00000070) 4317 #define RTC_TR_ST_0 ((uint32_t)0x00000010) 4318 #define RTC_TR_ST_1 ((uint32_t)0x00000020) 4319 #define RTC_TR_ST_2 ((uint32_t)0x00000040) 4320 #define RTC_TR_SU ((uint32_t)0x0000000F) 4321 #define RTC_TR_SU_0 ((uint32_t)0x00000001) 4322 #define RTC_TR_SU_1 ((uint32_t)0x00000002) 4323 #define RTC_TR_SU_2 ((uint32_t)0x00000004) 4324 #define RTC_TR_SU_3 ((uint32_t)0x00000008) 4325 4326 /******************** Bits definition for RTC_DR register *******************/ 4327 #define RTC_DR_YT ((uint32_t)0x00F00000) 4328 #define RTC_DR_YT_0 ((uint32_t)0x00100000) 4329 #define RTC_DR_YT_1 ((uint32_t)0x00200000) 4330 #define RTC_DR_YT_2 ((uint32_t)0x00400000) 4331 #define RTC_DR_YT_3 ((uint32_t)0x00800000) 4332 #define RTC_DR_YU ((uint32_t)0x000F0000) 4333 #define RTC_DR_YU_0 ((uint32_t)0x00010000) 4334 #define RTC_DR_YU_1 ((uint32_t)0x00020000) 4335 #define RTC_DR_YU_2 ((uint32_t)0x00040000) 4336 #define RTC_DR_YU_3 ((uint32_t)0x00080000) 4337 #define RTC_DR_WDU ((uint32_t)0x0000E000) 4338 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) 4339 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) 4340 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) 4341 #define RTC_DR_MT ((uint32_t)0x00001000) 4342 #define RTC_DR_MU ((uint32_t)0x00000F00) 4343 #define RTC_DR_MU_0 ((uint32_t)0x00000100) 4344 #define RTC_DR_MU_1 ((uint32_t)0x00000200) 4345 #define RTC_DR_MU_2 ((uint32_t)0x00000400) 4346 #define RTC_DR_MU_3 ((uint32_t)0x00000800) 4347 #define RTC_DR_DT ((uint32_t)0x00000030) 4348 #define RTC_DR_DT_0 ((uint32_t)0x00000010) 4349 #define RTC_DR_DT_1 ((uint32_t)0x00000020) 4350 #define RTC_DR_DU ((uint32_t)0x0000000F) 4351 #define RTC_DR_DU_0 ((uint32_t)0x00000001) 4352 #define RTC_DR_DU_1 ((uint32_t)0x00000002) 4353 #define RTC_DR_DU_2 ((uint32_t)0x00000004) 4354 #define RTC_DR_DU_3 ((uint32_t)0x00000008) 4355 4356 /******************** Bits definition for RTC_CR register *******************/ 4357 #define RTC_CR_COE ((uint32_t)0x00800000) 4358 #define RTC_CR_OSEL ((uint32_t)0x00600000) 4359 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) 4360 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) 4361 #define RTC_CR_POL ((uint32_t)0x00100000) 4362 #define RTC_CR_COSEL ((uint32_t)0x00080000) 4363 #define RTC_CR_BKP ((uint32_t)0x00040000) 4364 #define RTC_CR_SUB1H ((uint32_t)0x00020000) 4365 #define RTC_CR_ADD1H ((uint32_t)0x00010000) 4366 #define RTC_CR_TSIE ((uint32_t)0x00008000) 4367 #define RTC_CR_WUTIE ((uint32_t)0x00004000) 4368 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) 4369 #define RTC_CR_TSE ((uint32_t)0x00000800) 4370 #define RTC_CR_WUTE ((uint32_t)0x00000400) 4371 #define RTC_CR_ALRAE ((uint32_t)0x00000100) 4372 #define RTC_CR_FMT ((uint32_t)0x00000040) 4373 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) 4374 #define RTC_CR_REFCKON ((uint32_t)0x00000010) 4375 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) 4376 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) 4377 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) 4378 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) 4379 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) 4380 4381 /* Old bit definition maintained for legacy purpose */ 4382 #define RTC_CR_BCK RTC_CR_BKP 4383 #define RTC_CR_CALSEL RTC_CR_COSEL 4384 4385 /******************** Bits definition for RTC_ISR register ******************/ 4386 #define RTC_ISR_RECALPF ((uint32_t)0x00010000) 4387 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000) 4388 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) 4389 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) 4390 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) 4391 #define RTC_ISR_TSF ((uint32_t)0x00000800) 4392 #define RTC_ISR_WUTF ((uint32_t)0x00000400) 4393 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) 4394 #define RTC_ISR_INIT ((uint32_t)0x00000080) 4395 #define RTC_ISR_INITF ((uint32_t)0x00000040) 4396 #define RTC_ISR_RSF ((uint32_t)0x00000020) 4397 #define RTC_ISR_INITS ((uint32_t)0x00000010) 4398 #define RTC_ISR_SHPF ((uint32_t)0x00000008) 4399 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) 4400 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) 4401 4402 /******************** Bits definition for RTC_PRER register *****************/ 4403 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) 4404 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) 4405 4406 /******************** Bits definition for RTC_WUTR register *****************/ 4407 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) 4408 4409 /******************** Bits definition for RTC_ALRMAR register ***************/ 4410 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) 4411 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) 4412 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) 4413 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) 4414 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) 4415 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) 4416 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) 4417 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) 4418 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) 4419 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) 4420 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) 4421 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) 4422 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) 4423 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) 4424 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) 4425 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) 4426 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) 4427 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) 4428 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) 4429 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) 4430 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) 4431 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) 4432 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) 4433 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) 4434 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) 4435 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) 4436 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) 4437 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) 4438 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) 4439 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) 4440 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) 4441 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) 4442 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) 4443 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) 4444 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) 4445 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) 4446 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) 4447 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) 4448 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) 4449 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) 4450 4451 /******************** Bits definition for RTC_WPR register ******************/ 4452 #define RTC_WPR_KEY ((uint32_t)0x000000FF) 4453 4454 /******************** Bits definition for RTC_SSR register ******************/ 4455 #define RTC_SSR_SS ((uint32_t)0x0003FFFF) 4456 4457 /******************** Bits definition for RTC_SHIFTR register ***************/ 4458 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) 4459 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) 4460 4461 /******************** Bits definition for RTC_TSTR register *****************/ 4462 #define RTC_TSTR_PM ((uint32_t)0x00400000) 4463 #define RTC_TSTR_HT ((uint32_t)0x00300000) 4464 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) 4465 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) 4466 #define RTC_TSTR_HU ((uint32_t)0x000F0000) 4467 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) 4468 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) 4469 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) 4470 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) 4471 #define RTC_TSTR_MNT ((uint32_t)0x00007000) 4472 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) 4473 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) 4474 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) 4475 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) 4476 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) 4477 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) 4478 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) 4479 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) 4480 #define RTC_TSTR_ST ((uint32_t)0x00000070) 4481 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) 4482 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) 4483 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) 4484 #define RTC_TSTR_SU ((uint32_t)0x0000000F) 4485 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) 4486 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) 4487 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) 4488 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) 4489 4490 /******************** Bits definition for RTC_TSDR register *****************/ 4491 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) 4492 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) 4493 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) 4494 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) 4495 #define RTC_TSDR_MT ((uint32_t)0x00001000) 4496 #define RTC_TSDR_MU ((uint32_t)0x00000F00) 4497 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) 4498 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) 4499 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) 4500 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) 4501 #define RTC_TSDR_DT ((uint32_t)0x00000030) 4502 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) 4503 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) 4504 #define RTC_TSDR_DU ((uint32_t)0x0000000F) 4505 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) 4506 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) 4507 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) 4508 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) 4509 4510 /******************** Bits definition for RTC_TSSSR register ****************/ 4511 #define RTC_TSSSR_SS ((uint32_t)0x0003FFFF) 4512 4513 /******************** Bits definition for RTC_CALR register ******************/ 4514 #define RTC_CALR_CALP ((uint32_t)0x00008000) 4515 #define RTC_CALR_CALW8 ((uint32_t)0x00004000) 4516 #define RTC_CALR_CALW16 ((uint32_t)0x00002000) 4517 #define RTC_CALR_CALM ((uint32_t)0x000001FF) 4518 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) 4519 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) 4520 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) 4521 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) 4522 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) 4523 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) 4524 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) 4525 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) 4526 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) 4527 4528 /* Old Bits definition for RTC_CAL register maintained for legacy purpose */ 4529 #define RTC_CAL_CALP RTC_CALR_CALP 4530 #define RTC_CAL_CALW8 RTC_CALR_CALW8 4531 #define RTC_CAL_CALW16 RTC_CALR_CALW16 4532 #define RTC_CAL_CALM RTC_CALR_CALM 4533 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0 4534 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1 4535 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2 4536 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3 4537 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4 4538 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5 4539 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6 4540 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7 4541 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 4542 4543 /******************** Bits definition for RTC_TAFCR register ****************/ 4544 #define RTC_TAFCR_PC15MODE ((uint32_t)0x00800000) 4545 #define RTC_TAFCR_PC15VALUE ((uint32_t)0x00400000) 4546 #define RTC_TAFCR_PC14MODE ((uint32_t)0x00200000) 4547 #define RTC_TAFCR_PC14VALUE ((uint32_t)0x00100000) 4548 #define RTC_TAFCR_PC13MODE ((uint32_t)0x00080000) 4549 #define RTC_TAFCR_PC13VALUE ((uint32_t)0x00040000) 4550 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) 4551 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) 4552 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) 4553 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) 4554 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) 4555 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) 4556 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) 4557 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) 4558 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) 4559 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) 4560 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) 4561 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) 4562 #define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040) 4563 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) 4564 #define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010) 4565 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) 4566 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) 4567 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) 4568 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) 4569 4570 /* Old bit definition maintained for legacy purpose */ 4571 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE 4572 4573 /******************** Bits definition for RTC_ALRMASSR register *************/ 4574 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) 4575 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) 4576 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) 4577 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) 4578 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) 4579 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) 4580 4581 /******************** Bits definition for RTC_BKP0R register ****************/ 4582 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) 4583 4584 /******************** Bits definition for RTC_BKP1R register ****************/ 4585 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) 4586 4587 /******************** Bits definition for RTC_BKP2R register ****************/ 4588 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) 4589 4590 /******************** Bits definition for RTC_BKP3R register ****************/ 4591 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) 4592 4593 /******************** Bits definition for RTC_BKP4R register ****************/ 4594 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) 4595 4596 /******************************************************************************/ 4597 /* */ 4598 /* Serial Peripheral Interface (SPI) */ 4599 /* */ 4600 /******************************************************************************/ 4601 /******************* Bit definition for SPI_CR1 register ********************/ 4602 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */ 4603 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */ 4604 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */ 4605 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */ 4606 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */ 4607 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */ 4608 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */ 4609 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */ 4610 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */ 4611 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */ 4612 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */ 4613 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */ 4614 #define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */ 4615 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */ 4616 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */ 4617 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */ 4618 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */ 4619 4620 /******************* Bit definition for SPI_CR2 register ********************/ 4621 #define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */ 4622 #define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */ 4623 #define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */ 4624 #define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */ 4625 #define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */ 4626 #define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */ 4627 #define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */ 4628 #define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */ 4629 #define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */ 4630 #define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */ 4631 #define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */ 4632 #define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */ 4633 #define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */ 4634 #define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */ 4635 #define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */ 4636 #define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */ 4637 4638 /******************** Bit definition for SPI_SR register ********************/ 4639 #define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */ 4640 #define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */ 4641 #define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */ 4642 #define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */ 4643 #define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */ 4644 #define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */ 4645 #define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */ 4646 #define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */ 4647 #define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */ 4648 #define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */ 4649 #define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */ 4650 #define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */ 4651 #define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */ 4652 #define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */ 4653 #define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */ 4654 4655 /******************** Bit definition for SPI_DR register ********************/ 4656 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */ 4657 4658 /******************* Bit definition for SPI_CRCPR register ******************/ 4659 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */ 4660 4661 /****************** Bit definition for SPI_RXCRCR register ******************/ 4662 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */ 4663 4664 /****************** Bit definition for SPI_TXCRCR register ******************/ 4665 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */ 4666 4667 /****************** Bit definition for SPI_I2SCFGR register *****************/ 4668 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */ 4669 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */ 4670 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */ 4671 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */ 4672 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */ 4673 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */ 4674 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */ 4675 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */ 4676 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */ 4677 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 4678 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */ 4679 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */ 4680 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */ 4681 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */ 4682 4683 /****************** Bit definition for SPI_I2SPR register *******************/ 4684 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */ 4685 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */ 4686 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */ 4687 4688 /******************************************************************************/ 4689 /* */ 4690 /* System Configuration (SYSCFG) */ 4691 /* */ 4692 /******************************************************************************/ 4693 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 4694 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */ 4695 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */ 4696 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */ 4697 #define SYSCFG_CFGR1_IRDA_ENV_SEL ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */ 4698 #define SYSCFG_CFGR1_IRDA_ENV_SEL_0 ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */ 4699 #define SYSCFG_CFGR1_IRDA_ENV_SEL_1 ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */ 4700 #define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)*/ 4701 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */ 4702 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */ 4703 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */ 4704 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */ 4705 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */ 4706 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for STM32F072) */ 4707 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for STM32F072) */ 4708 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */ 4709 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */ 4710 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ 4711 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ 4712 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) */ 4713 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for STM32F072) */ 4714 #define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F091 devices) */ 4715 #define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042, STM32F072 and STM32F091 devices) */ 4716 #define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for STM32F072) */ 4717 #define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for STM32F072) */ 4718 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for STM32F072) */ 4719 #define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for STM32F072) */ 4720 #define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for STM32F072) */ 4721 #define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for STM32F072) */ 4722 #define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for STM32F072) */ 4723 4724 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 4725 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ 4726 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ 4727 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ 4728 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ 4729 4730 /** 4731 * @brief EXTI0 configuration 4732 */ 4733 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ 4734 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ 4735 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ 4736 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ 4737 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ 4738 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ 4739 4740 /** 4741 * @brief EXTI1 configuration 4742 */ 4743 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ 4744 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ 4745 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ 4746 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ 4747 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ 4748 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ 4749 4750 /** 4751 * @brief EXTI2 configuration 4752 */ 4753 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ 4754 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ 4755 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ 4756 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ 4757 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ 4758 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ 4759 4760 /** 4761 * @brief EXTI3 configuration 4762 */ 4763 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ 4764 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ 4765 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ 4766 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ 4767 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ 4768 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ 4769 4770 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 4771 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ 4772 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ 4773 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ 4774 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ 4775 4776 /** 4777 * @brief EXTI4 configuration 4778 */ 4779 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ 4780 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ 4781 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ 4782 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ 4783 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ 4784 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ 4785 4786 /** 4787 * @brief EXTI5 configuration 4788 */ 4789 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ 4790 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ 4791 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ 4792 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ 4793 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ 4794 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ 4795 4796 /** 4797 * @brief EXTI6 configuration 4798 */ 4799 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ 4800 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ 4801 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ 4802 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ 4803 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ 4804 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ 4805 4806 /** 4807 * @brief EXTI7 configuration 4808 */ 4809 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ 4810 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ 4811 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ 4812 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ 4813 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ 4814 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ 4815 4816 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 4817 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ 4818 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ 4819 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ 4820 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ 4821 4822 /** 4823 * @brief EXTI8 configuration 4824 */ 4825 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ 4826 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ 4827 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ 4828 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ 4829 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ 4830 4831 /** 4832 * @brief EXTI9 configuration 4833 */ 4834 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ 4835 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ 4836 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ 4837 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ 4838 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ 4839 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ 4840 4841 /** 4842 * @brief EXTI10 configuration 4843 */ 4844 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ 4845 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ 4846 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ 4847 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */ 4848 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */ 4849 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ 4850 4851 /** 4852 * @brief EXTI11 configuration 4853 */ 4854 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ 4855 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ 4856 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ 4857 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ 4858 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ 4859 4860 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 4861 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ 4862 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ 4863 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ 4864 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ 4865 4866 /** 4867 * @brief EXTI12 configuration 4868 */ 4869 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ 4870 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ 4871 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ 4872 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ 4873 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ 4874 4875 /** 4876 * @brief EXTI13 configuration 4877 */ 4878 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ 4879 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ 4880 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ 4881 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ 4882 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ 4883 4884 /** 4885 * @brief EXTI14 configuration 4886 */ 4887 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ 4888 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ 4889 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ 4890 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ 4891 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ 4892 4893 /** 4894 * @brief EXTI15 configuration 4895 */ 4896 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ 4897 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ 4898 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ 4899 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ 4900 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ 4901 4902 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 4903 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */ 4904 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */ 4905 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */ 4906 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */ 4907 4908 /* Old Bit definition maintained for legacy purpose */ 4909 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF 4910 4911 /***************** Bit definition for SYSCFG_xxx ISR Wrapper register ****************/ 4912 #define SYSCFG_ITLINE0_SR_EWDG ((uint32_t)0x00000001) /*!< EWDG interrupt */ 4913 #define SYSCFG_ITLINE1_SR_PVDOUT ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */ 4914 #define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ 4915 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ 4916 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ 4917 #define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ 4918 #define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ 4919 #define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ 4920 #define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ 4921 #define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ 4922 #define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ 4923 #define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ 4924 #define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ 4925 #define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ 4926 #define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ 4927 #define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ 4928 #define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ 4929 #define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ 4930 #define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ 4931 #define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ 4932 #define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ 4933 #define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ 4934 #define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ 4935 #define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ 4936 #define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ 4937 #define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ 4938 #define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ 4939 #define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ 4940 #define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ 4941 #define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ 4942 #define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ 4943 #define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ 4944 #define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ 4945 #define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ 4946 #define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ 4947 #define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ 4948 #define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ 4949 #define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ 4950 #define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ 4951 #define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ 4952 #define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ 4953 #define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ 4954 #define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ 4955 #define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ 4956 #define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ 4957 #define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ 4958 #define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ 4959 #define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ 4960 #define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ 4961 #define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ 4962 #define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ 4963 #define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ 4964 #define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ 4965 #define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ 4966 #define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ 4967 #define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ 4968 #define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ 4969 #define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ 4970 #define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ 4971 #define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ 4972 #define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ 4973 #define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ 4974 #define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ 4975 #define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ 4976 #define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ 4977 #define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ 4978 #define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ 4979 #define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ 4980 #define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ 4981 #define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ 4982 4983 /******************************************************************************/ 4984 /* */ 4985 /* Timers (TIM) */ 4986 /* */ 4987 /******************************************************************************/ 4988 /******************* Bit definition for TIM_CR1 register ********************/ 4989 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */ 4990 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */ 4991 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */ 4992 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */ 4993 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */ 4994 4995 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ 4996 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */ 4997 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */ 4998 4999 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */ 5000 5001 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */ 5002 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */ 5003 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */ 5004 5005 /******************* Bit definition for TIM_CR2 register ********************/ 5006 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */ 5007 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */ 5008 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */ 5009 5010 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */ 5011 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */ 5012 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */ 5013 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */ 5014 5015 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */ 5016 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */ 5017 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */ 5018 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */ 5019 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */ 5020 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */ 5021 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */ 5022 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */ 5023 5024 /******************* Bit definition for TIM_SMCR register *******************/ 5025 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */ 5026 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */ 5027 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */ 5028 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */ 5029 5030 #define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selection */ 5031 5032 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */ 5033 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */ 5034 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */ 5035 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */ 5036 5037 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */ 5038 5039 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */ 5040 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */ 5041 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */ 5042 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */ 5043 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */ 5044 5045 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */ 5046 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */ 5047 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */ 5048 5049 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */ 5050 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */ 5051 5052 /******************* Bit definition for TIM_DIER register *******************/ 5053 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */ 5054 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */ 5055 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */ 5056 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */ 5057 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */ 5058 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */ 5059 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */ 5060 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */ 5061 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */ 5062 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */ 5063 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */ 5064 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */ 5065 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */ 5066 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */ 5067 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */ 5068 5069 /******************** Bit definition for TIM_SR register ********************/ 5070 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */ 5071 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */ 5072 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */ 5073 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */ 5074 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */ 5075 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */ 5076 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */ 5077 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */ 5078 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */ 5079 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */ 5080 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */ 5081 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */ 5082 5083 /******************* Bit definition for TIM_EGR register ********************/ 5084 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */ 5085 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */ 5086 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */ 5087 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */ 5088 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */ 5089 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */ 5090 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */ 5091 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */ 5092 5093 /****************** Bit definition for TIM_CCMR1 register *******************/ 5094 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 5095 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */ 5096 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */ 5097 5098 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */ 5099 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */ 5100 5101 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 5102 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */ 5103 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */ 5104 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */ 5105 5106 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */ 5107 5108 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 5109 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */ 5110 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */ 5111 5112 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */ 5113 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */ 5114 5115 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 5116 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */ 5117 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */ 5118 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */ 5119 5120 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */ 5121 5122 /*----------------------------------------------------------------------------*/ 5123 5124 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 5125 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ 5126 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ 5127 5128 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 5129 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */ 5130 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */ 5131 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */ 5132 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */ 5133 5134 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 5135 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ 5136 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ 5137 5138 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 5139 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */ 5140 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */ 5141 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */ 5142 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */ 5143 5144 /****************** Bit definition for TIM_CCMR2 register *******************/ 5145 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 5146 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */ 5147 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */ 5148 5149 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */ 5150 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */ 5151 5152 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 5153 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */ 5154 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */ 5155 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */ 5156 5157 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */ 5158 5159 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 5160 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */ 5161 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */ 5162 5163 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */ 5164 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */ 5165 5166 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 5167 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */ 5168 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */ 5169 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */ 5170 5171 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */ 5172 5173 /*----------------------------------------------------------------------------*/ 5174 5175 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 5176 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */ 5177 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */ 5178 5179 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 5180 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */ 5181 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */ 5182 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */ 5183 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */ 5184 5185 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 5186 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */ 5187 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */ 5188 5189 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 5190 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */ 5191 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */ 5192 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */ 5193 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */ 5194 5195 /******************* Bit definition for TIM_CCER register *******************/ 5196 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */ 5197 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */ 5198 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */ 5199 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */ 5200 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */ 5201 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */ 5202 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */ 5203 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */ 5204 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */ 5205 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */ 5206 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */ 5207 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */ 5208 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */ 5209 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */ 5210 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */ 5211 5212 /******************* Bit definition for TIM_CNT register ********************/ 5213 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */ 5214 5215 /******************* Bit definition for TIM_PSC register ********************/ 5216 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */ 5217 5218 /******************* Bit definition for TIM_ARR register ********************/ 5219 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */ 5220 5221 /******************* Bit definition for TIM_RCR register ********************/ 5222 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */ 5223 5224 /******************* Bit definition for TIM_CCR1 register *******************/ 5225 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */ 5226 5227 /******************* Bit definition for TIM_CCR2 register *******************/ 5228 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */ 5229 5230 /******************* Bit definition for TIM_CCR3 register *******************/ 5231 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */ 5232 5233 /******************* Bit definition for TIM_CCR4 register *******************/ 5234 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */ 5235 5236 /******************* Bit definition for TIM_BDTR register *******************/ 5237 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 5238 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */ 5239 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */ 5240 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */ 5241 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */ 5242 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */ 5243 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */ 5244 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */ 5245 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */ 5246 5247 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */ 5248 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */ 5249 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */ 5250 5251 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */ 5252 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */ 5253 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */ 5254 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */ 5255 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */ 5256 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */ 5257 5258 /******************* Bit definition for TIM_DCR register ********************/ 5259 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */ 5260 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */ 5261 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */ 5262 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */ 5263 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */ 5264 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */ 5265 5266 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */ 5267 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */ 5268 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */ 5269 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */ 5270 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */ 5271 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */ 5272 5273 /******************* Bit definition for TIM_DMAR register *******************/ 5274 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */ 5275 5276 /******************* Bit definition for TIM_OR register *********************/ 5277 #define TIM14_OR_TI1_RMP ((uint16_t)0x0003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */ 5278 #define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */ 5279 #define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */ 5280 5281 5282 /******************************************************************************/ 5283 /* */ 5284 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 5285 /* */ 5286 /******************************************************************************/ 5287 /****************** Bit definition for USART_CR1 register *******************/ 5288 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */ 5289 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */ 5290 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ 5291 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ 5292 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ 5293 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ 5294 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ 5295 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */ 5296 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ 5297 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ 5298 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ 5299 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */ 5300 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */ 5301 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */ 5302 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */ 5303 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */ 5304 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 5305 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ 5306 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ 5307 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ 5308 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ 5309 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ 5310 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 5311 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */ 5312 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */ 5313 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */ 5314 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */ 5315 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */ 5316 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */ 5317 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */ 5318 5319 /****************** Bit definition for USART_CR2 register *******************/ 5320 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */ 5321 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ 5322 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ 5323 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ 5324 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ 5325 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ 5326 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ 5327 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ 5328 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ 5329 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ 5330 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ 5331 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */ 5332 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */ 5333 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */ 5334 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */ 5335 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */ 5336 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/ 5337 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 5338 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */ 5339 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */ 5340 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */ 5341 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */ 5342 5343 /****************** Bit definition for USART_CR3 register *******************/ 5344 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ 5345 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ 5346 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ 5347 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ 5348 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */ 5349 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */ 5350 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ 5351 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ 5352 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ 5353 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ 5354 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ 5355 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */ 5356 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */ 5357 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */ 5358 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */ 5359 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */ 5360 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 5361 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */ 5362 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */ 5363 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */ 5364 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 5365 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */ 5366 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */ 5367 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */ 5368 5369 /****************** Bit definition for USART_BRR register *******************/ 5370 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ 5371 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ 5372 5373 /****************** Bit definition for USART_GTPR register ******************/ 5374 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */ 5375 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */ 5376 5377 5378 /******************* Bit definition for USART_RTOR register *****************/ 5379 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */ 5380 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */ 5381 5382 /******************* Bit definition for USART_RQR register ******************/ 5383 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ 5384 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ 5385 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ 5386 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ 5387 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ 5388 5389 /******************* Bit definition for USART_ISR register ******************/ 5390 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */ 5391 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */ 5392 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */ 5393 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ 5394 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ 5395 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ 5396 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ 5397 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ 5398 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ 5399 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */ 5400 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */ 5401 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */ 5402 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */ 5403 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */ 5404 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */ 5405 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */ 5406 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */ 5407 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */ 5408 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */ 5409 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */ 5410 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */ 5411 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */ 5412 5413 /******************* Bit definition for USART_ICR register ******************/ 5414 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */ 5415 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */ 5416 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */ 5417 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */ 5418 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */ 5419 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */ 5420 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */ 5421 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */ 5422 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */ 5423 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */ 5424 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */ 5425 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */ 5426 5427 /******************* Bit definition for USART_RDR register ******************/ 5428 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */ 5429 5430 /******************* Bit definition for USART_TDR register ******************/ 5431 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */ 5432 5433 /******************************************************************************/ 5434 /* */ 5435 /* Window WATCHDOG (WWDG) */ 5436 /* */ 5437 /******************************************************************************/ 5438 5439 /******************* Bit definition for WWDG_CR register ********************/ 5440 #define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 5441 #define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ 5442 #define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ 5443 #define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ 5444 #define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ 5445 #define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ 5446 #define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ 5447 #define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ 5448 5449 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ 5450 5451 /******************* Bit definition for WWDG_CFR register *******************/ 5452 #define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ 5453 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ 5454 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ 5455 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ 5456 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ 5457 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ 5458 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ 5459 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ 5460 5461 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ 5462 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ 5463 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ 5464 5465 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ 5466 5467 /******************* Bit definition for WWDG_SR register ********************/ 5468 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ 5469 5470 #if defined (STM32F091) 5471 /******************************************************************************/ 5472 /* For a painless codes migration between the STM32F0xx device product */ 5473 /* lines, the aliases defined below are put in place to overcome the */ 5474 /* differences in the interrupt handlers and IRQn definitions. */ 5475 /* No need to update developed interrupt code when moving across */ 5476 /* product lines within the same STM32L0 Family */ 5477 /******************************************************************************/ 5478 5479 /* Aliases for __IRQn */ 5480 #define PVD_IRQn PVD_VDDIO2_IRQn 5481 #define RCC_IRQn RCC_CRS_IRQn 5482 #define TS_IRQn TSC_IRQn 5483 #define DMA1_Channel1_IRQn DMA1_Ch1_IRQn 5484 #define DMA1_Channel2_3_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn 5485 #define DMA1_Channel4_5_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn 5486 #define DMA1_Channel4_5_6_7_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn 5487 #define ADC1_IRQn ADC1_COMP_IRQn 5488 #define USART3_4_IRQn USART3_8_IRQn 5489 #define CEC_IRQn CEC_CAN_IRQn 5490 5491 /* Aliases for __IRQHandler */ 5492 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler 5493 #define RCC_IRQHandler RCC_CRS_IRQHandler 5494 #define TS_IRQHandler TSC_IRQHandler 5495 #define DMA1_Channel1_IRQHandler DMA1_Ch1_IRQHandler 5496 #define DMA1_Channel2_3_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 5497 #define DMA1_Channel4_5_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler 5498 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler 5499 #define ADC1_IRQHandler ADC1_COMP_IRQHandler 5500 #define USART3_4_IRQHandler USART3_8_IRQHandler 5501 #define CEC_IRQHandler CEC_CAN_IRQHandler 5502 5503 #elif defined (STM32F072) 5504 /* Aliases for __IRQn */ 5505 #define PVD_IRQn PVD_VDDIO2_IRQn 5506 #define RCC_IRQn RCC_CRS_IRQn 5507 #define TS_IRQn TSC_IRQn 5508 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5509 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5510 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn 5511 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_6_7_IRQn 5512 #define ADC1_IRQn ADC1_COMP_IRQn 5513 #define USART3_8_IRQn USART3_4_IRQn 5514 #define CEC_IRQn CEC_CAN_IRQn 5515 5516 /* Aliases for __IRQHandler */ 5517 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler 5518 #define RCC_IRQHandler RCC_CRS_IRQHandler 5519 #define TS_IRQHandler TSC_IRQHandler 5520 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5521 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5522 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler 5523 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler 5524 #define ADC1_IRQHandler ADC1_COMP_IRQHandler 5525 #define USART3_8_IRQHandler USART3_4_IRQHandler 5526 #define CEC_IRQHandler CEC_CAN_IRQHandler 5527 5528 #elif defined (STM32F051) 5529 /* Aliases for __IRQn */ 5530 #define PVD_VDDIO2_IRQn PVD_IRQn 5531 #define RCC_CRS_IRQn RCC_IRQn 5532 #define TSC_IRQn TS_IRQn 5533 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5534 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5535 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5536 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5537 #define ADC1_IRQn ADC1_COMP_IRQn 5538 #define CEC_CAN_IRQn CEC_IRQn 5539 5540 /* Aliases for __IRQHandler */ 5541 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler 5542 #define RCC_CRS_IRQHandler RCC_IRQHandler 5543 #define TSC_IRQHandler TS_IRQHandler 5544 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5545 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5546 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5547 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5548 #define ADC1_IRQHandler ADC1_COMP_IRQHandler 5549 #define CEC_CAN_IRQHandler CEC_IRQHandler 5550 5551 #elif defined (STM32F042) 5552 /* Aliases for __IRQn */ 5553 #define PVD_IRQn PVD_VDDIO2_IRQn 5554 #define RCC_IRQn RCC_CRS_IRQn 5555 #define TS_IRQn TSC_IRQn 5556 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5557 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5558 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn 5559 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_6_7_IRQn 5560 #define ADC1_COMP_IRQn ADC1_IRQn 5561 #define CEC_IRQn CEC_CAN_IRQn 5562 5563 /* Aliases for __IRQHandler */ 5564 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler 5565 #define RCC_IRQHandler RCC_CRS_IRQHandler 5566 #define TS_IRQHandler TSC_IRQHandler 5567 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5568 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5569 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler 5570 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler 5571 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5572 #define CEC_IRQHandler CEC_CAN_IRQHandler 5573 5574 #elif defined (STM32F031) 5575 /* Aliases for __IRQn */ 5576 #define PVD_VDDIO2_IRQn PVD_IRQn 5577 #define RCC_CRS_IRQn RCC_IRQn 5578 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5579 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5580 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5581 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5582 #define ADC1_COMP_IRQn ADC1_IRQn 5583 5584 /* Aliases for __IRQHandler */ 5585 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler 5586 #define RCC_CRS_IRQHandler RCC_IRQHandler 5587 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5588 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5589 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5590 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5591 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5592 5593 #elif defined (STM32F030) 5594 /* Aliases for __IRQn */ 5595 #define RCC_CRS_IRQn RCC_IRQn 5596 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5597 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5598 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5599 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5600 #define ADC1_COMP_IRQn ADC1_IRQn 5601 5602 /* Aliases for __IRQHandler */ 5603 #define RCC_CRS_IRQHandler RCC_IRQHandler 5604 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5605 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5606 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5607 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5608 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5609 5610 #elif defined (STM32F070xB) 5611 /* Aliases for __IRQn */ 5612 #define RCC_CRS_IRQn RCC_IRQn 5613 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5614 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5615 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5616 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5617 #define ADC1_COMP_IRQn ADC1_IRQn 5618 #define TIM6_DAC_IRQn TIM6_IRQn 5619 #define USART3_8_IRQn USART3_4_IRQn 5620 #define USART3_6_IRQn USART3_4_IRQn 5621 5622 /* Aliases for __IRQHandler */ 5623 #define RCC_CRS_IRQHandler RCC_IRQHandler 5624 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5625 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5626 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5627 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5628 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5629 #define TIM6_DAC_IRQHandler TIM6_IRQHandler 5630 #define USART3_8_IRQHandler USART3_4_IRQHandler 5631 #define USART3_6_IRQHandler USART3_4_IRQHandler 5632 5633 #elif defined (STM32F070x6) 5634 /* Aliases for __IRQn */ 5635 #define RCC_CRS_IRQn RCC_IRQn 5636 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5637 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5638 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5639 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5640 #define ADC1_COMP_IRQn ADC1_IRQn 5641 5642 /* Aliases for __IRQHandler */ 5643 #define RCC_CRS_IRQHandler RCC_IRQHandler 5644 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5645 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5646 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5647 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5648 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5649 5650 #elif defined (STM32F030xC) 5651 /* Aliases for __IRQn */ 5652 #define RCC_CRS_IRQn RCC_IRQn 5653 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn 5654 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn 5655 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn 5656 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn 5657 #define ADC1_COMP_IRQn ADC1_IRQn 5658 #define TIM6_DAC_IRQn TIM6_IRQn 5659 #define USART3_8_IRQn USART3_6_IRQn 5660 #define USART3_4_IRQn USART3_6_IRQn 5661 5662 /* Aliases for __IRQHandler */ 5663 #define RCC_CRS_IRQHandler RCC_IRQHandler 5664 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler 5665 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler 5666 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler 5667 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler 5668 #define ADC1_COMP_IRQHandler ADC1_IRQHandler 5669 #define TIM6_DAC_IRQHandler TIM6_IRQHandler 5670 #define USART3_8_IRQHandler USART3_6_IRQHandler 5671 #define USART3_4_IRQHandler USART3_6_IRQHandler 5672 5673 #endif /* STM32F091 */ 5674 /** 5675 * @} 5676 */ 5677 5678 /** 5679 * @} 5680 */ 5681 5682 #ifdef USE_STDPERIPH_DRIVER 5683 #include "stm32f0xx_conf.h" 5684 #endif 5685 5686 /** @addtogroup Exported_macro 5687 * @{ 5688 */ 5689 /** 5690 * @} 5691 */ 5692 5693 #ifdef __cplusplus 5694 } 5695 #endif 5696 5697 #endif /* __STM32F0XX_H */ 5698 5699 /** 5700 * @} 5701 */ 5702 5703 /** 5704 * @} 5705 */ 5706 5707 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 5708