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Searched refs:RECIP_V2DF_DIV (Results 1 – 25 of 27) sorted by relevance

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/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rs6000/
H A Drs6000.c217 RECIP_V2DF_DIV = 0x008, enumerator
227 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
246 | RECIP_V2DF_DIV) },
248 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3270 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/rs6000/
H A Drs6000.c215 RECIP_V2DF_DIV = 0x008, enumerator
225 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
244 | RECIP_V2DF_DIV) },
246 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3240 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/rs6000/
H A Drs6000.c213 RECIP_V2DF_DIV = 0x008, enumerator
223 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
242 | RECIP_V2DF_DIV) },
244 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3265 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/rs6000/
H A Drs6000.c215 RECIP_V2DF_DIV = 0x008, enumerator
225 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
244 | RECIP_V2DF_DIV) },
246 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3246 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc11/gcc-11.2.0/gcc/config/rs6000/
H A Drs6000.c213 RECIP_V2DF_DIV = 0x008, enumerator
223 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
242 | RECIP_V2DF_DIV) },
244 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3265 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/rs6000/
H A Drs6000.c213 RECIP_V2DF_DIV = 0x008, enumerator
223 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
242 | RECIP_V2DF_DIV) },
244 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3265 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc10/gcc-10.3.0/gcc/config/rs6000/
H A Drs6000.c215 RECIP_V2DF_DIV = 0x008, enumerator
225 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
244 | RECIP_V2DF_DIV) },
246 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3246 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/mingw32-gcc/gcc-4.8.1/gcc/config/rs6000/
H A Drs6000.c249 RECIP_V2DF_DIV = 0x008, enumerator
259 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
278 | RECIP_V2DF_DIV) },
280 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
2251 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc48/gcc-4.8.5/gcc/config/rs6000/
H A Drs6000.c252 RECIP_V2DF_DIV = 0x008, enumerator
262 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
281 | RECIP_V2DF_DIV) },
283 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
2907 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/rs6000/
H A Drs6000.c269 RECIP_V2DF_DIV = 0x008, enumerator
279 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
298 | RECIP_V2DF_DIV) },
300 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
2937 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c305 RECIP_V2DF_DIV = 0x008, enumerator
315 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
334 | RECIP_V2DF_DIV) },
336 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3797 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc9/gcc-9.4.0/gcc/config/rs6000/
H A Drs6000.c302 RECIP_V2DF_DIV = 0x008, enumerator
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
331 | RECIP_V2DF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3556 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/rs6000/
H A Drs6000.c260 RECIP_V2DF_DIV = 0x008, enumerator
270 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
289 | RECIP_V2DF_DIV) },
291 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3634 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/rs6000/
H A Drs6000.c305 RECIP_V2DF_DIV = 0x008, enumerator
315 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
334 | RECIP_V2DF_DIV) },
336 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3797 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c305 RECIP_V2DF_DIV = 0x008, enumerator
315 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
334 | RECIP_V2DF_DIV) },
336 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3797 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c305 RECIP_V2DF_DIV = 0x008, enumerator
315 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
334 | RECIP_V2DF_DIV) },
336 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3797 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/rs6000/
H A Drs6000.c305 RECIP_V2DF_DIV = 0x008, enumerator
315 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
334 | RECIP_V2DF_DIV) },
336 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3797 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/rs6000/
H A Drs6000.c302 RECIP_V2DF_DIV = 0x008, enumerator
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
331 | RECIP_V2DF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3556 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/rs6000/
H A Drs6000.c302 RECIP_V2DF_DIV = 0x008, enumerator
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
331 | RECIP_V2DF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3556 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc8/gcc-8.5.0/gcc/config/rs6000/
H A Drs6000.c305 RECIP_V2DF_DIV = 0x008, enumerator
315 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
334 | RECIP_V2DF_DIV) },
336 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3797 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/rs6000/
H A Drs6000.c260 RECIP_V2DF_DIV = 0x008, enumerator
270 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
289 | RECIP_V2DF_DIV) },
291 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3634 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c284 RECIP_V2DF_DIV = 0x008, enumerator
294 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V2DF_DIV) },
315 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3849 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c284 RECIP_V2DF_DIV = 0x008, enumerator
294 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V2DF_DIV) },
315 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3849 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c284 RECIP_V2DF_DIV = 0x008, enumerator
294 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V2DF_DIV) },
315 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3849 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/powerpcspe/
H A Dpowerpcspe.c284 RECIP_V2DF_DIV = 0x008, enumerator
294 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V2DF_DIV) },
315 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
3849 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0) in rs6000_init_hard_regno_mode_ok()

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