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/dports/devel/llvm80/llvm-8.0.1.src/test/CodeGen/PowerPC/
H A Dvarargs.ll25 ; P32: lwz [[REG6:r[0-9]+]], 8(r3)
26 ; P32: add [[REG6]], [[REG6]], [[REG4]]
29 ; P32: ori [[REG6]], [[REG2]], 0
32 ; P32: lwz r3, 0([[REG6]])
/dports/games/libretro-mu/Mu-ff746b8/src/armv5te/
H A Dthumb_interpreter.cpp111 #define REG6 arm.reg[insn >> 6 & 7] in cpu_thumb_loop() macro
119 … CASE_x2(0x18): /* ADD Rd, Rn, Rm */ set_nz_flags(REG0 = add(REG3, REG6, 0, true)); break; in cpu_thumb_loop()
120 … CASE_x2(0x1A): /* SUB Rd, Rn, Rm */ set_nz_flags(REG0 = add(REG3, ~REG6, 1, true)); break; in cpu_thumb_loop()
180 CASE_x2(0x50): /* STR Rd, [Rn, Rm] */ write_word(REG3 + REG6, REG0); break; in cpu_thumb_loop()
181 CASE_x2(0x52): /* STRH Rd, [Rn, Rm] */ write_half(REG3 + REG6, REG0); break; in cpu_thumb_loop()
182 CASE_x2(0x54): /* STRB Rd, [Rn, Rm] */ write_byte(REG3 + REG6, REG0); break; in cpu_thumb_loop()
183 … CASE_x2(0x56): /* LDRSB Rd, [Rn, Rm] */ REG0 = (int8_t)read_byte(REG3 + REG6); break; in cpu_thumb_loop()
184 CASE_x2(0x58): /* LDR Rd, [Rn, Rm] */ REG0 = read_word(REG3 + REG6); break; in cpu_thumb_loop()
185 CASE_x2(0x5A): /* LDRH Rd, [Rn, Rm] */ REG0 = read_half(REG3 + REG6); break; in cpu_thumb_loop()
186 CASE_x2(0x5C): /* LDRB Rd, [Rn, Rm] */ REG0 = read_byte(REG3 + REG6); break; in cpu_thumb_loop()
[all …]
/dports/devel/tinygo/tinygo-0.14.1/lib/picolibc/newlib/libc/machine/mips/
H A Dmemcpy.S227 # define REG6 t6 macro
232 # define REG6 ta2 macro
485 C_LD REG6,UNIT(6)(a1)
498 C_ST REG6,UNIT(6)(a0)
507 C_LD REG6,UNIT(14)(a1)
518 C_ST REG6,UNIT(14)(a0)
543 C_LD REG6,UNIT(6)(a1)
552 C_ST REG6,UNIT(6)(a0)
722 C_ST REG6,UNIT(6)(a0)
747 C_ST REG6,UNIT(14)(a0)
[all …]
/dports/devel/arm-none-eabi-newlib/newlib-2.4.0/newlib/libc/machine/mips/
H A Dmemcpy.S227 # define REG6 t6 macro
232 # define REG6 ta2 macro
485 C_LD REG6,UNIT(6)(a1)
498 C_ST REG6,UNIT(6)(a0)
507 C_LD REG6,UNIT(14)(a1)
518 C_ST REG6,UNIT(14)(a0)
543 C_LD REG6,UNIT(6)(a1)
552 C_ST REG6,UNIT(6)(a0)
722 C_ST REG6,UNIT(6)(a0)
747 C_ST REG6,UNIT(14)(a0)
[all …]
/dports/emulators/vice/vice-3.5/src/lib/libffmpeg/libavcodec/x86/
H A Dxvididct_sse2.c117 # define REG6 ROW6 macro
135 # define REG6 "%%xmm6" macro
235 MOV_32_ONLY ROW6", "REG6" \n\t" \
237 "pmulhw "REG6", %%xmm7 \n\t" \
240 "psubsw "REG6", %%xmm5 \n\t" \
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
56 ; CHECK-DISABLE: [[REG6]] += r0
57 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
65 ; CHECK-DISABLE: [[REG6]] += r0
66 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
56 ; CHECK-DISABLE: [[REG6]] += r0
57 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
65 ; CHECK-DISABLE: [[REG6]] += r0
66 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/graphics/llvm-mesa/llvm-13.0.1.src/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
56 ; CHECK-DISABLE: [[REG6]] += r0
57 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
65 ; CHECK-DISABLE: [[REG6]] += r0
66 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/sysutils/xvidcap/xvidcap-1.1.7/ffmpeg/libavcodec/i386/
H A Didct_sse2_xvid.c114 # define REG6 ROW6 macro
132 # define REG6 "%%xmm6" macro
232 MOV_32_ONLY ROW6", "REG6" \n\t" \
234 "pmulhw "REG6", %%xmm7 \n\t" \
237 "psubsw "REG6", %%xmm5 \n\t" \
/dports/emulators/libretro-vice/vice-libretro-5725415/vice/src/lib/libffmpeg/libavcodec/x86/
H A Dxvididct_sse2.c117 # define REG6 ROW6 macro
135 # define REG6 "%%xmm6" macro
235 MOV_32_ONLY ROW6", "REG6" \n\t" \
237 "pmulhw "REG6", %%xmm7 \n\t" \
240 "psubsw "REG6", %%xmm5 \n\t" \
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
56 ; CHECK-DISABLE: [[REG6]] += r0
57 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
65 ; CHECK-DISABLE: [[REG6]] += r0
66 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
56 ; CHECK-DISABLE: [[REG6]] += r0
57 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
65 ; CHECK-DISABLE: [[REG6]] += r0
66 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
52 ; CHECK-DISABLE: r0 = [[REG6]]
56 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
59 ; CHECK-DISABLE: r0 = [[REG6]]
63 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
52 ; CHECK-DISABLE: r0 = [[REG6]]
56 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
59 ; CHECK-DISABLE: r0 = [[REG6]]
63 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/CodeGen/BPF/
H A Dadjust-opt-speculative1.ll44 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
48 ; CHECK: [[REG6]] += r0
50 ; CHECK: r0 = [[REG6]]
52 ; CHECK-DISABLE: r0 = [[REG6]]
56 ; CHECK-DISABLE: r0 = [[REG6]]
H A Dadjust-opt-speculative2.ll46 ; CHECK-COMMON: [[REG6:r[0-9]+]] = r1
52 ; CHECK: [[REG6]] += r0
54 ; CHECK: r0 = [[REG6]]
59 ; CHECK-DISABLE: r0 = [[REG6]]
63 ; CHECK-DISABLE: r0 = [[REG6]]
/dports/games/libretro-mame2000/mame2000-libretro-e364a15/src/machine/
H A Dmathbox.c24 #define REG6 mb_reg [0x06] macro
64 case 0x0c: mb_result = REG6 = data; break; in WRITE_HANDLER()
183 REGf = REG6; /* step counter */ in WRITE_HANDLER()
223 while (--REG6 >= 0); in WRITE_HANDLER()
/dports/games/libretro-mame2003/mame2003-libretro-4358db4/src/machine/
H A Dmathbox.c23 #define REG6 mb_reg [0x06] macro
63 case 0x0c: mb_result = REG6 = data; break; in WRITE_HANDLER()
182 REGf = REG6; /* step counter */ in WRITE_HANDLER()
222 while (--REG6 >= 0); in WRITE_HANDLER()

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