RXDLYOVRDEN (reference) in projects: dports

Searched refs:RXDLYOVRDEN (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/
H A D	whiterabbit_gtxe2_channel_wrapper_gt.vhd	`598 RXDLYOVRDEN => tied_to_ground_i,`
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/
H A D	whiterabbit_gtpe2_channel_wrapper_gt.vhd	`728 RXDLYOVRDEN => tied_to_ground_i,`
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A D	cells_xtra.v	`13031 input RXDLYOVRDEN; port 13592 input RXDLYOVRDEN; port 14141 input RXDLYOVRDEN; port 14922 input RXDLYOVRDEN; port 15868 input RXDLYOVRDEN; port 16898 input RXDLYOVRDEN; port 17900 input RXDLYOVRDEN; port`