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Searched refs:SH_REG_LSW_OFFSET (Results 1 – 25 of 74) sorted by relevance

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/dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
H A Dsh.c1192 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; in sh_print_operand()
1197 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
1208 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
/dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
H A Dsh.c1202 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; in sh_print_operand()
1207 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
1218 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
/dports/lang/gcc9/gcc-9.4.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
H A Dsh.c1205 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; in sh_print_operand()
1210 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
1221 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
/dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/sh/
H A Dsh.h401 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
H A Dsh.c1190 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; in sh_print_operand()
1195 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
1206 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
/dports/devel/avr-gcc/gcc-10.2.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
H A Dsh.c1202 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; in sh_print_operand()
1207 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
1218 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
/dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
H A Dsh.c1202 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET; in sh_print_operand()
1207 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
1218 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET); in sh_print_operand()
/dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/sh/
H A Dsh.h401 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc10/gcc-10.3.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc8/gcc-8.5.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc11/gcc-11.2.0/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc10-devel/gcc-10-20211008/gcc/config/sh/
H A Dsh.h403 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gnat_util/gcc-6-20180516/gcc/config/sh/
H A Dsh.h433 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/sh/
H A Dsh.h433 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro
/dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/sh/
H A Dsh.h411 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) macro

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