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Searched refs:SMX_APE_BASE (Results 1 – 25 of 140) sorted by relevance

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/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-omap3/
H A Dcpu.h450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-omap3/
H A Dcpu.h450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-omap3/
H A Dcpu.h450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/arch/arm/include/asm/arch-omap3/
H A Dcpu.h450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/arch/arm/include/asm/arch-omap3/
H A Dcpu.h450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-omap3/
H A Dcpu.h450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/arch/arm/include/asm/arch-omap3/
H A Dcpu.h450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/include/asm/arch-omap3/
H A Dcpu.h439 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
440 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
441 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
442 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)

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