1 /* 2 * (C) Copyright 2006-2008 3 * Texas Instruments, <www.ti.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #ifndef _CPU_H 26 #define _CPU_H 27 28 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 29 #include <asm/types.h> 30 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 31 32 /* Register offsets of common modules */ 33 /* Control */ 34 #ifndef __KERNEL_STRICT_NAMES 35 #ifndef __ASSEMBLY__ 36 struct ctrl { 37 u8 res1[0xC0]; 38 u16 gpmc_nadv_ale; /* 0xC0 */ 39 u16 gpmc_noe; /* 0xC2 */ 40 u16 gpmc_nwe; /* 0xC4 */ 41 u8 res2[0x22A]; 42 u32 status; /* 0x2F0 */ 43 u32 gpstatus; /* 0x2F4 */ 44 u8 res3[0x08]; 45 u32 rpubkey_0; /* 0x300 */ 46 u32 rpubkey_1; /* 0x304 */ 47 u32 rpubkey_2; /* 0x308 */ 48 u32 rpubkey_3; /* 0x30C */ 49 u32 rpubkey_4; /* 0x310 */ 50 u8 res4[0x04]; 51 u32 randkey_0; /* 0x318 */ 52 u32 randkey_1; /* 0x31C */ 53 u32 randkey_2; /* 0x320 */ 54 u32 randkey_3; /* 0x324 */ 55 u8 res5[0x124]; 56 u32 ctrl_omap_stat; /* 0x44C */ 57 }; 58 #else /* __ASSEMBLY__ */ 59 #define CONTROL_STATUS 0x2F0 60 #endif /* __ASSEMBLY__ */ 61 #endif /* __KERNEL_STRICT_NAMES */ 62 63 /* cpu type */ 64 #define OMAP3503 0x5c00 65 #define OMAP3515 0x1c00 66 #define OMAP3525 0x4c00 67 #define OMAP3530 0x0c00 68 69 #ifndef __KERNEL_STRICT_NAMES 70 #ifndef __ASSEMBLY__ 71 struct ctrl_id { 72 u8 res1[0x4]; 73 u32 idcode; /* 0x04 */ 74 u32 prod_id; /* 0x08 */ 75 u8 res2[0x0C]; 76 u32 die_id_0; /* 0x18 */ 77 u32 die_id_1; /* 0x1C */ 78 u32 die_id_2; /* 0x20 */ 79 u32 die_id_3; /* 0x24 */ 80 }; 81 #endif /* __ASSEMBLY__ */ 82 #endif /* __KERNEL_STRICT_NAMES */ 83 84 /* device type */ 85 #define DEVICE_MASK (0x7 << 8) 86 #define SYSBOOT_MASK 0x1F 87 #define TST_DEVICE 0x0 88 #define EMU_DEVICE 0x1 89 #define HS_DEVICE 0x2 90 #define GP_DEVICE 0x3 91 92 #define GPMC_BASE (OMAP34XX_GPMC_BASE) 93 #define GPMC_CONFIG_CS0 0x60 94 #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) 95 96 #ifndef __KERNEL_STRICT_NAMES 97 #ifndef __ASSEMBLY__ 98 struct gpmc_cs { 99 u32 config1; /* 0x00 */ 100 u32 config2; /* 0x04 */ 101 u32 config3; /* 0x08 */ 102 u32 config4; /* 0x0C */ 103 u32 config5; /* 0x10 */ 104 u32 config6; /* 0x14 */ 105 u32 config7; /* 0x18 */ 106 u32 nand_cmd; /* 0x1C */ 107 u32 nand_adr; /* 0x20 */ 108 u32 nand_dat; /* 0x24 */ 109 u8 res[8]; /* blow up to 0x30 byte */ 110 }; 111 112 struct gpmc { 113 u8 res1[0x10]; 114 u32 sysconfig; /* 0x10 */ 115 u8 res2[0x4]; 116 u32 irqstatus; /* 0x18 */ 117 u32 irqenable; /* 0x1C */ 118 u8 res3[0x20]; 119 u32 timeout_control; /* 0x40 */ 120 u8 res4[0xC]; 121 u32 config; /* 0x50 */ 122 u32 status; /* 0x54 */ 123 u8 res5[0x8]; /* 0x58 */ 124 struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ 125 u8 res6[0x14]; /* 0x1E0 */ 126 u32 ecc_config; /* 0x1F4 */ 127 u32 ecc_control; /* 0x1F8 */ 128 u32 ecc_size_config; /* 0x1FC */ 129 u32 ecc1_result; /* 0x200 */ 130 u32 ecc2_result; /* 0x204 */ 131 u32 ecc3_result; /* 0x208 */ 132 u32 ecc4_result; /* 0x20C */ 133 u32 ecc5_result; /* 0x210 */ 134 u32 ecc6_result; /* 0x214 */ 135 u32 ecc7_result; /* 0x218 */ 136 u32 ecc8_result; /* 0x21C */ 137 u32 ecc9_result; /* 0x220 */ 138 }; 139 140 /* Used for board specific gpmc initialization */ 141 extern struct gpmc *gpmc_cfg; 142 143 #else /* __ASSEMBLY__ */ 144 #define GPMC_CONFIG1 0x00 145 #define GPMC_CONFIG2 0x04 146 #define GPMC_CONFIG3 0x08 147 #define GPMC_CONFIG4 0x0C 148 #define GPMC_CONFIG5 0x10 149 #define GPMC_CONFIG6 0x14 150 #define GPMC_CONFIG7 0x18 151 #endif /* __ASSEMBLY__ */ 152 #endif /* __KERNEL_STRICT_NAMES */ 153 154 /* GPMC Mapping */ 155 #define FLASH_BASE 0x10000000 /* NOR flash, */ 156 /* aligned to 256 Meg */ 157 #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ 158 /* aligned to 64 Meg */ 159 #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ 160 /* aligned to 256 Meg */ 161 #define DEBUG_BASE 0x08000000 /* debug board */ 162 #define NAND_BASE 0x30000000 /* NAND addr */ 163 /* (actual size small port) */ 164 #define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ 165 #define ONENAND_MAP 0x20000000 /* OneNand addr */ 166 /* (actual size small port) */ 167 /* SMS */ 168 #ifndef __KERNEL_STRICT_NAMES 169 #ifndef __ASSEMBLY__ 170 struct sms { 171 u8 res1[0x10]; 172 u32 sysconfig; /* 0x10 */ 173 u8 res2[0x34]; 174 u32 rg_att0; /* 0x48 */ 175 u8 res3[0x84]; 176 u32 class_arb0; /* 0xD0 */ 177 }; 178 #endif /* __ASSEMBLY__ */ 179 #endif /* __KERNEL_STRICT_NAMES */ 180 181 #define BURSTCOMPLETE_GROUP7 (0x1 << 31) 182 183 /* SDRC */ 184 #ifndef __KERNEL_STRICT_NAMES 185 #ifndef __ASSEMBLY__ 186 struct sdrc_cs { 187 u32 mcfg; /* 0x80 || 0xB0 */ 188 u32 mr; /* 0x84 || 0xB4 */ 189 u8 res1[0x4]; 190 u32 emr2; /* 0x8C || 0xBC */ 191 u8 res2[0x14]; 192 u32 rfr_ctrl; /* 0x84 || 0xD4 */ 193 u32 manual; /* 0xA8 || 0xD8 */ 194 u8 res3[0x4]; 195 }; 196 197 struct sdrc_actim { 198 u32 ctrla; /* 0x9C || 0xC4 */ 199 u32 ctrlb; /* 0xA0 || 0xC8 */ 200 }; 201 202 struct sdrc { 203 u8 res1[0x10]; 204 u32 sysconfig; /* 0x10 */ 205 u32 status; /* 0x14 */ 206 u8 res2[0x28]; 207 u32 cs_cfg; /* 0x40 */ 208 u32 sharing; /* 0x44 */ 209 u8 res3[0x18]; 210 u32 dlla_ctrl; /* 0x60 */ 211 u32 dlla_status; /* 0x64 */ 212 u32 dllb_ctrl; /* 0x68 */ 213 u32 dllb_status; /* 0x6C */ 214 u32 power; /* 0x70 */ 215 u8 res4[0xC]; 216 struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ 217 }; 218 219 /* EMIF4 */ 220 typedef struct emif4 { 221 unsigned int sdram_sts; 222 unsigned int sdram_config; 223 unsigned int res1; 224 unsigned int sdram_refresh_ctrl; 225 unsigned int sdram_refresh_ctrl_shdw; 226 unsigned int sdram_time1; 227 unsigned int sdram_time1_shdw; 228 unsigned int sdram_time2; 229 unsigned int sdram_time2_shdw; 230 unsigned int sdram_time3; 231 unsigned int sdram_time3_shdw; 232 unsigned char res2[8]; 233 unsigned int sdram_pwr_mgmt; 234 unsigned int sdram_pwr_mgmt_shdw; 235 unsigned char res3[32]; 236 unsigned int sdram_iodft_tlgc; 237 unsigned char res4[128]; 238 unsigned int ddr_phyctrl1; 239 unsigned int ddr_phyctrl1_shdw; 240 unsigned int ddr_phyctrl2; 241 } emif4_t; 242 243 #endif /* __ASSEMBLY__ */ 244 #endif /* __KERNEL_STRICT_NAMES */ 245 246 #define DLLPHASE_90 (0x1 << 1) 247 #define LOADDLL (0x1 << 2) 248 #define ENADLL (0x1 << 3) 249 #define DLL_DELAY_MASK 0xFF00 250 #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) 251 252 #define PAGEPOLICY_HIGH (0x1 << 0) 253 #define SRFRONRESET (0x1 << 7) 254 #define PWDNEN (0x1 << 2) 255 #define WAKEUPPROC (0x1 << 26) 256 257 #define DDR_SDRAM (0x1 << 0) 258 #define DEEPPD (0x1 << 3) 259 #define B32NOT16 (0x1 << 4) 260 #define BANKALLOCATION (0x2 << 6) 261 #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ 262 #define ADDRMUXLEGACY (0x1 << 19) 263 #define CASWIDTH_10BITS (0x5 << 20) 264 #define RASWIDTH_13BITS (0x2 << 24) 265 #define BURSTLENGTH4 (0x2 << 0) 266 #define CASL3 (0x3 << 4) 267 #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) 268 #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) 269 #define ARE_ARCV_1 (0x1 << 0) 270 #define ARCV (0x4e2 << 8) /* Autorefresh count */ 271 #define OMAP34XX_SDRC_CS0 0x80000000 272 #define OMAP34XX_SDRC_CS1 0xA0000000 273 #define CMD_NOP 0x0 274 #define CMD_PRECHARGE 0x1 275 #define CMD_AUTOREFRESH 0x2 276 #define CMD_ENTR_PWRDOWN 0x3 277 #define CMD_EXIT_PWRDOWN 0x4 278 #define CMD_ENTR_SRFRSH 0x5 279 #define CMD_CKE_HIGH 0x6 280 #define CMD_CKE_LOW 0x7 281 #define SOFTRESET (0x1 << 1) 282 #define SMART_IDLE (0x2 << 3) 283 #define REF_ON_IDLE (0x1 << 6) 284 285 /* timer regs offsets (32 bit regs) */ 286 287 #ifndef __KERNEL_STRICT_NAMES 288 #ifndef __ASSEMBLY__ 289 struct gptimer { 290 u32 tidr; /* 0x00 r */ 291 u8 res[0xc]; 292 u32 tiocp_cfg; /* 0x10 rw */ 293 u32 tistat; /* 0x14 r */ 294 u32 tisr; /* 0x18 rw */ 295 u32 tier; /* 0x1c rw */ 296 u32 twer; /* 0x20 rw */ 297 u32 tclr; /* 0x24 rw */ 298 u32 tcrr; /* 0x28 rw */ 299 u32 tldr; /* 0x2c rw */ 300 u32 ttgr; /* 0x30 rw */ 301 u32 twpc; /* 0x34 r*/ 302 u32 tmar; /* 0x38 rw*/ 303 u32 tcar1; /* 0x3c r */ 304 u32 tcicr; /* 0x40 rw */ 305 u32 tcar2; /* 0x44 r */ 306 }; 307 #endif /* __ASSEMBLY__ */ 308 #endif /* __KERNEL_STRICT_NAMES */ 309 310 /* enable sys_clk NO-prescale /1 */ 311 #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 312 313 /* Watchdog */ 314 #ifndef __KERNEL_STRICT_NAMES 315 #ifndef __ASSEMBLY__ 316 struct watchdog { 317 u8 res1[0x34]; 318 u32 wwps; /* 0x34 r */ 319 u8 res2[0x10]; 320 u32 wspr; /* 0x48 rw */ 321 }; 322 #endif /* __ASSEMBLY__ */ 323 #endif /* __KERNEL_STRICT_NAMES */ 324 325 #define WD_UNLOCK1 0xAAAA 326 #define WD_UNLOCK2 0x5555 327 328 /* PRCM */ 329 #define PRCM_BASE 0x48004000 330 331 #ifndef __KERNEL_STRICT_NAMES 332 #ifndef __ASSEMBLY__ 333 struct prcm { 334 u32 fclken_iva2; /* 0x00 */ 335 u32 clken_pll_iva2; /* 0x04 */ 336 u8 res1[0x1c]; 337 u32 idlest_pll_iva2; /* 0x24 */ 338 u8 res2[0x18]; 339 u32 clksel1_pll_iva2 ; /* 0x40 */ 340 u32 clksel2_pll_iva2; /* 0x44 */ 341 u8 res3[0x8bc]; 342 u32 clken_pll_mpu; /* 0x904 */ 343 u8 res4[0x1c]; 344 u32 idlest_pll_mpu; /* 0x924 */ 345 u8 res5[0x18]; 346 u32 clksel1_pll_mpu; /* 0x940 */ 347 u32 clksel2_pll_mpu; /* 0x944 */ 348 u8 res6[0xb8]; 349 u32 fclken1_core; /* 0xa00 */ 350 u8 res7[0xc]; 351 u32 iclken1_core; /* 0xa10 */ 352 u32 iclken2_core; /* 0xa14 */ 353 u8 res8[0x28]; 354 u32 clksel_core; /* 0xa40 */ 355 u8 res9[0xbc]; 356 u32 fclken_gfx; /* 0xb00 */ 357 u8 res10[0xc]; 358 u32 iclken_gfx; /* 0xb10 */ 359 u8 res11[0x2c]; 360 u32 clksel_gfx; /* 0xb40 */ 361 u8 res12[0xbc]; 362 u32 fclken_wkup; /* 0xc00 */ 363 u8 res13[0xc]; 364 u32 iclken_wkup; /* 0xc10 */ 365 u8 res14[0xc]; 366 u32 idlest_wkup; /* 0xc20 */ 367 u8 res15[0x1c]; 368 u32 clksel_wkup; /* 0xc40 */ 369 u8 res16[0xbc]; 370 u32 clken_pll; /* 0xd00 */ 371 u8 res17[0x1c]; 372 u32 idlest_ckgen; /* 0xd20 */ 373 u8 res18[0x1c]; 374 u32 clksel1_pll; /* 0xd40 */ 375 u32 clksel2_pll; /* 0xd44 */ 376 u32 clksel3_pll; /* 0xd48 */ 377 u8 res19[0xb4]; 378 u32 fclken_dss; /* 0xe00 */ 379 u8 res20[0xc]; 380 u32 iclken_dss; /* 0xe10 */ 381 u8 res21[0x2c]; 382 u32 clksel_dss; /* 0xe40 */ 383 u8 res22[0xbc]; 384 u32 fclken_cam; /* 0xf00 */ 385 u8 res23[0xc]; 386 u32 iclken_cam; /* 0xf10 */ 387 u8 res24[0x2c]; 388 u32 clksel_cam; /* 0xf40 */ 389 u8 res25[0xbc]; 390 u32 fclken_per; /* 0x1000 */ 391 u8 res26[0xc]; 392 u32 iclken_per; /* 0x1010 */ 393 u8 res27[0x2c]; 394 u32 clksel_per; /* 0x1040 */ 395 u8 res28[0xfc]; 396 u32 clksel1_emu; /* 0x1140 */ 397 }; 398 #else /* __ASSEMBLY__ */ 399 #define CM_CLKSEL_CORE 0x48004a40 400 #define CM_CLKSEL_GFX 0x48004b40 401 #define CM_CLKSEL_WKUP 0x48004c40 402 #define CM_CLKEN_PLL 0x48004d00 403 #define CM_CLKSEL1_PLL 0x48004d40 404 #define CM_CLKSEL1_EMU 0x48005140 405 #endif /* __ASSEMBLY__ */ 406 #endif /* __KERNEL_STRICT_NAMES */ 407 408 #define PRM_BASE 0x48306000 409 410 #ifndef __KERNEL_STRICT_NAMES 411 #ifndef __ASSEMBLY__ 412 struct prm { 413 u8 res1[0xd40]; 414 u32 clksel; /* 0xd40 */ 415 u8 res2[0x50c]; 416 u32 rstctrl; /* 0x1250 */ 417 u8 res3[0x1c]; 418 u32 clksrc_ctrl; /* 0x1270 */ 419 }; 420 #else /* __ASSEMBLY__ */ 421 #define PRM_RSTCTRL 0x48307250 422 #endif /* __ASSEMBLY__ */ 423 #endif /* __KERNEL_STRICT_NAMES */ 424 425 #define SYSCLKDIV_1 (0x1 << 6) 426 #define SYSCLKDIV_2 (0x1 << 7) 427 428 #define CLKSEL_GPT1 (0x1 << 0) 429 430 #define EN_GPT1 (0x1 << 0) 431 #define EN_32KSYNC (0x1 << 2) 432 433 #define ST_WDT2 (0x1 << 5) 434 435 #define ST_MPU_CLK (0x1 << 0) 436 437 #define ST_CORE_CLK (0x1 << 0) 438 439 #define ST_PERIPH_CLK (0x1 << 1) 440 441 #define ST_IVA2_CLK (0x1 << 0) 442 443 #define RESETDONE (0x1 << 0) 444 445 #define TCLR_ST (0x1 << 0) 446 #define TCLR_AR (0x1 << 1) 447 #define TCLR_PRE (0x1 << 5) 448 449 /* SMX-APE */ 450 #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) 451 #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) 452 #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) 453 #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) 454 455 #ifndef __KERNEL_STRICT_NAMES 456 #ifndef __ASSEMBLY__ 457 struct pm { 458 u8 res1[0x48]; 459 u32 req_info_permission_0; /* 0x48 */ 460 u8 res2[0x4]; 461 u32 read_permission_0; /* 0x50 */ 462 u8 res3[0x4]; 463 u32 wirte_permission_0; /* 0x58 */ 464 u8 res4[0x4]; 465 u32 addr_match_1; /* 0x58 */ 466 u8 res5[0x4]; 467 u32 req_info_permission_1; /* 0x68 */ 468 u8 res6[0x14]; 469 u32 addr_match_2; /* 0x80 */ 470 }; 471 #endif /*__ASSEMBLY__ */ 472 #endif /* __KERNEL_STRICT_NAMES */ 473 474 /* Permission values for registers -Full fledged permissions to all */ 475 #define UNLOCK_1 0xFFFFFFFF 476 #define UNLOCK_2 0x00000000 477 #define UNLOCK_3 0x0000FFFF 478 479 #define NOT_EARLY 0 480 481 /* I2C base */ 482 #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) 483 #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) 484 #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) 485 486 #endif /* _CPU_H */ 487