| /dports/emulators/qemu60/qemu-6.0.0/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
397 # SVE stack frame size
434 ### SVE Element Count Group
436 # SVE element count
497 # SVE vector table lookup
632 # SVE predicate test
635 # SVE predicate initialize
638 # SVE initialize FFR
676 # SVE predicate count
911 # SVE load vector register
[all …]
|
| /dports/emulators/qemu5/qemu-5.2.0/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
397 # SVE stack frame size
434 ### SVE Element Count Group
436 # SVE element count
497 # SVE vector table lookup
632 # SVE predicate test
635 # SVE predicate initialize
638 # SVE initialize FFR
676 # SVE predicate count
911 # SVE load vector register
[all …]
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
397 # SVE stack frame size
437 ### SVE Element Count Group
439 # SVE element count
500 # SVE vector table lookup
635 # SVE predicate test
638 # SVE predicate initialize
641 # SVE initialize FFR
679 # SVE predicate count
914 # SVE load vector register
[all …]
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
396 # SVE stack frame size
436 ### SVE Element Count Group
438 # SVE element count
499 # SVE vector table lookup
634 # SVE predicate test
637 # SVE predicate initialize
640 # SVE initialize FFR
678 # SVE predicate count
913 # SVE load vector register
[all …]
|
| /dports/emulators/qemu42/qemu-4.2.1/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
397 # SVE stack frame size
437 ### SVE Element Count Group
439 # SVE element count
500 # SVE vector table lookup
635 # SVE predicate test
638 # SVE predicate initialize
641 # SVE initialize FFR
679 # SVE predicate count
914 # SVE load vector register
[all …]
|
| /dports/emulators/qemu-utils/qemu-4.2.1/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
397 # SVE stack frame size
437 ### SVE Element Count Group
439 # SVE element count
500 # SVE vector table lookup
635 # SVE predicate test
638 # SVE predicate initialize
641 # SVE initialize FFR
679 # SVE predicate count
914 # SVE load vector register
[all …]
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
397 # SVE stack frame size
437 ### SVE Element Count Group
439 # SVE element count
500 # SVE vector table lookup
635 # SVE predicate test
638 # SVE predicate initialize
641 # SVE initialize FFR
679 # SVE predicate count
914 # SVE load vector register
[all …]
|
| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
458 # SVE stack frame size
495 ### SVE Element Count Group
497 # SVE element count
562 # SVE vector table lookup
713 # SVE predicate test
716 # SVE predicate initialize
719 # SVE initialize FFR
757 # SVE predicate count
1096 # SVE load vector register
[all …]
|
| /dports/emulators/qemu/qemu-6.2.0/target/arm/ |
| H A D | sve.decode | 1 # AArch64 SVE instruction descriptions
458 # SVE stack frame size
495 ### SVE Element Count Group
497 # SVE element count
562 # SVE vector table lookup
713 # SVE predicate test
716 # SVE predicate initialize
719 # SVE initialize FFR
757 # SVE predicate count
1096 # SVE load vector register
[all …]
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/test/Analysis/CostModel/AArch64/ |
| H A D | mem-op-cost-model.ll | 1 ; Check memory cost model action for fixed vector SVE and Neon
3 ; CHECK-NEON has same performance as CHECK-SVE-128
13 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
14 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
15 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
23 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
24 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
25 ; CHECK-SVE-512: Cost Model: Found an estimated cost of 1 for instruction:
33 ; CHECK-SVE-128: Cost Model: Found an estimated cost of 1 for instruction:
34 ; CHECK-SVE-256: Cost Model: Found an estimated cost of 1 for instruction:
[all …]
|
| /dports/lang/gnu-apl/apl-1.8/src/testcases/ |
| H A D | Quad_SVE.tc | 6 ⎕SVE←0
7 ⎕SVE
10 ⎕SVE←1.9
11 100 ⎕SVO 'OS' ◊ ⎕SVE
17 ⎕SVE←0.2
18 ⎕SVE
|
| /dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/aarch64/ |
| H A D | illegal-sve2.l | 11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
37 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnt z32\.b,z0\.h,z0\.h'
39 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnt z0\.b,z0\.h,z32\.h'
58 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesd z32\.b,z0\.b,z0\.b'
65 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aese z32\.b,z0\.b,z0\.b'
[all …]
|
| H A D | sve-movprfx_28.l | 4 .*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
5 .*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
6 .*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
7 .*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
8 .*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
|
| /dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/aarch64/ |
| H A D | illegal-sve2.l | 11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
37 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnt z32\.b,z0\.h,z0\.h'
39 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnt z0\.b,z0\.h,z32\.h'
58 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesd z32\.b,z0\.b,z0\.b'
65 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aese z32\.b,z0\.b,z0\.b'
[all …]
|
| H A D | sve-movprfx_28.l | 4 .*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
5 .*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
6 .*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
7 .*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
8 .*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
|
| /dports/devel/binutils/binutils-2.37/gas/testsuite/gas/aarch64/ |
| H A D | illegal-sve2.l | 11 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
13 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
19 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
21 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
28 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
30 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
37 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnt z32\.b,z0\.h,z0\.h'
39 [^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnt z0\.b,z0\.h,z32\.h'
58 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesd z32\.b,z0\.b,z0\.b'
65 [^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aese z32\.b,z0\.b,z0\.b'
[all …]
|
| H A D | sve-movprfx_28.l | 4 .*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
5 .*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
6 .*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
7 .*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
8 .*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
|
| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/ada/libgnarl/ |
| H A D | s-osinte__vxworks.ads | 50 package SVE renames System.VxWorks.Ext; packspec
62 subtype STATUS is SVE.STATUS;
63 subtype BOOL is SVE.BOOL;
64 subtype vx_freq_t is SVE.vx_freq_t;
210 subtype t_id is SVE.t_id;
220 function getpid return t_id renames SVE.getpid;
380 SVE.Set_Time_Slice;
419 subtype SEM_ID is SVE.SEM_ID;
502 renames SVE.taskCpuAffinitySet;
507 renames SVE.taskMaskAffinitySet;
[all …]
|