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Searched refs:SYS_FPGA_CSPR_FINAL (Results 1 – 25 of 181) sorted by relevance

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/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-sopine/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-rpi/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-chip/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/include/configs/
H A Dls1088aqds.h180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ macro
232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL

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