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Searched refs:SubOp0 (Results 1 – 25 of 28) sorted by relevance

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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16592 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16594 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16596 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16821 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16823 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16825 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16176 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16178 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16180 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16847 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16849 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16851 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16176 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16178 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16180 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1645 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
1646 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1614 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
1615 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1582 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
1583 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16807 SDValue SubOp0 = Sub.getOperand(0);
16809 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) &&
16811 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0),
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16807 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16809 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16811 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16807 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16809 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16811 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16964 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16966 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16968 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16807 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16809 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16811 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16807 SDValue SubOp0 = Sub.getOperand(0); in combineTRUNCATE() local
16809 if ((SubOp0.getOpcode() == ISD::ZERO_EXTEND) && in combineTRUNCATE()
16811 return DCI.DAG.getNode(PPCISD::VABSD, dl, VT, SubOp0.getOperand(0), in combineTRUNCATE()
/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1821 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
1822 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1821 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
1822 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1821 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
1822 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2018 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2019 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2021 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2022 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2277 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2278 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2409 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2410 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2409 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2410 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2610 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2611 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2610 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2611 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2610 SDValue SubOp0 = RHS.getOperand(0); in emitConditionalComparison() local
2611 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in emitConditionalComparison()

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