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Searched refs:TCG_TARGET_HAS_rem_i32 (Results 1 – 25 of 116) sorted by relevance

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/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/arm/
H A Dtcg-target.h88 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/arm/
H A Dtcg-target.h88 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/mips/
H A Dtcg-target.h100 #define TCG_TARGET_HAS_rem_i32 1 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/ppc/
H A Dtcg-target.h56 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/mips/
H A Dtcg-target.h100 #define TCG_TARGET_HAS_rem_i32 1
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/ppc/
H A Dtcg-target.h56 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/aarch64/
H A Dtcg-target.h49 #define TCG_TARGET_HAS_rem_i32 1 macro
/dports/emulators/unicorn/unicorn-1.0.2/qemu/tcg/aarch64/
H A Dtcg-target.h49 #define TCG_TARGET_HAS_rem_i32 1 macro
/dports/emulators/qemu60/qemu-6.0.0/tcg/arm/
H A Dtcg-target.h126 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu-utils/qemu-4.2.1/tcg/arm/
H A Dtcg-target.h126 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu5/qemu-5.2.0/tcg/arm/
H A Dtcg-target.h126 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu-guest-agent/qemu-5.0.1/tcg/arm/
H A Dtcg-target.h126 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu42/qemu-4.2.1/tcg/arm/
H A Dtcg-target.h126 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/arm/
H A Dtcg-target.h125 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/tcg/arm/
H A Dtcg-target.h126 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/tci/
H A Dtcg-target.h66 #define TCG_TARGET_HAS_rem_i32 1 macro
/dports/emulators/qemu/qemu-6.2.0/tcg/tci/
H A Dtcg-target.h66 #define TCG_TARGET_HAS_rem_i32 1 macro
/dports/emulators/qemu60/qemu-6.0.0/tcg/tci/
H A Dtcg-target.h65 #define TCG_TARGET_HAS_rem_i32 1 macro
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/tcg/ppc/
H A Dtcg-target.h61 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/arm/
H A Dtcg-target.h125 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/tcg/sparc/
H A Dtcg-target.h95 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu/qemu-6.2.0/tcg/arm/
H A Dtcg-target.h125 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu/qemu-6.2.0/tcg/sparc/
H A Dtcg-target.h95 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/qemu60/qemu-6.0.0/tcg/sparc/
H A Dtcg-target.h94 #define TCG_TARGET_HAS_rem_i32 0 macro
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/tcg/
H A Dtcg-opc.h78 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
79 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))

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