/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 170 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 170 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 170 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 170 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 157 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 170 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 170 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/emulators/qemu/qemu-6.2.0/roms/ipxe/src/drivers/net/tg3/ |
H A D | tg3_hw.c | 1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset() 1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset() 1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset() 1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset() 1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset() 1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset() [all …]
|
H A D | tg3.h | 170 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/net/ethernet/broadcom/ |
H A D | tg3.c | 9511 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_tx_rcbs_disable() 9513 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_tx_rcbs_disable() 9516 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_tx_rcbs_disable() 9518 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable() 9520 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable() 9521 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_tx_rcbs_disable() 9554 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; in tg3_rx_ret_rcbs_disable() 9560 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rx_ret_rcbs_disable() 9562 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable() 9564 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable() [all …]
|
H A D | tg3.h | 28 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/net/ethernet/broadcom/ |
H A D | tg3.c | 9511 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_tx_rcbs_disable() 9513 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_tx_rcbs_disable() 9516 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_tx_rcbs_disable() 9518 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable() 9520 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable() 9521 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_tx_rcbs_disable() 9554 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; in tg3_rx_ret_rcbs_disable() 9560 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rx_ret_rcbs_disable() 9562 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable() 9564 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable() [all …]
|
H A D | tg3.h | 28 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/net/ethernet/broadcom/ |
H A D | tg3.c | 9511 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_tx_rcbs_disable() 9513 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_tx_rcbs_disable() 9516 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_tx_rcbs_disable() 9518 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable() 9520 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_tx_rcbs_disable() 9521 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_tx_rcbs_disable() 9554 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; in tg3_rx_ret_rcbs_disable() 9560 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rx_ret_rcbs_disable() 9562 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable() 9564 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rx_ret_rcbs_disable() [all …]
|
H A D | tg3.h | 28 #define TG3_BDINFO_SIZE 0x10UL macro
|
/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/drivers/net/ |
H A D | tg3.h | 93 #define TG3_BDINFO_SIZE 0x10UL macro
|
H A D | tg3.c | 2020 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE) in tg3_setup_hw() 2039 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) { in tg3_setup_hw()
|