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Searched refs:TXUSRCLK2 (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/
H A Dwhiterabbit_gtpe2_channel_wrapper_gt.vhd599 TXPI_PPMCLK_SEL => ("TXUSRCLK2"),
847 TXUSRCLK2 => TXUSRCLK2_IN,
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/
H A Dwhiterabbit_gtxe2_channel_wrapper_gt.vhd724 TXUSRCLK2 => TXUSRCLK2_IN,
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_xtra.v10364 input TXUSRCLK2; port
12540 input TXUSRCLK2; port
13120 input TXUSRCLK2; port
13679 input TXUSRCLK2; port
14209 input TXUSRCLK2; port
15045 input TXUSRCLK2; port
15988 input TXUSRCLK2; port
17020 input TXUSRCLK2; port
18018 input TXUSRCLK2; port