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Searched refs:TX_MARGIN_FULL_4 (Results 1 – 3 of 3) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtx/
H A Dwhiterabbit_gtxe2_channel_wrapper_gt.vhd425 TX_MARGIN_FULL_4 => ("1000000"),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/white_rabbit/wr_cores_v4_2/platform/xilinx/wr_gtp_phy/family7-gtp/
H A Dwhiterabbit_gtpe2_channel_wrapper_gt.vhd513 TX_MARGIN_FULL_4 => ("1000000"),
/dports/cad/yosys/yosys-yosys-0.12/techlibs/xilinx/
H A Dcells_xtra.v12401 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant
12861 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant
13469 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant
14000 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant
14698 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant
15630 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant
16622 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant
17633 parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; constant