/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 78 const TargetRegisterClass *UseRC = NULL; in EmitCopyFromReg() local 107 if (!UseRC) in EmitCopyFromReg() 108 UseRC = RC; in EmitCopyFromReg() 110 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 114 UseRC = ComRC; in EmitCopyFromReg() 131 } else if (UseRC) { in EmitCopyFromReg() 132 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); in EmitCopyFromReg() 133 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 105 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 110 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 140 if (!UseRC) in EmitCopyFromReg() 141 UseRC = RC; in EmitCopyFromReg() 144 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 148 UseRC = ComRC; in EmitCopyFromReg() 164 } else if (UseRC) { in EmitCopyFromReg() 165 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 167 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 103 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 138 if (!UseRC) in EmitCopyFromReg() 139 UseRC = RC; in EmitCopyFromReg() 142 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 146 UseRC = ComRC; in EmitCopyFromReg() 162 } else if (UseRC) { in EmitCopyFromReg() 163 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 165 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 105 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 110 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 140 if (!UseRC) in EmitCopyFromReg() 141 UseRC = RC; in EmitCopyFromReg() 144 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 148 UseRC = ComRC; in EmitCopyFromReg() 164 } else if (UseRC) { in EmitCopyFromReg() 165 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 167 DstRC = UseRC; in EmitCopyFromReg()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 103 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 138 if (!UseRC) in EmitCopyFromReg() 139 UseRC = RC; in EmitCopyFromReg() 142 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 146 UseRC = ComRC; in EmitCopyFromReg() 162 } else if (UseRC) { in EmitCopyFromReg() 163 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 165 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 103 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 138 if (!UseRC) in EmitCopyFromReg() 139 UseRC = RC; in EmitCopyFromReg() 142 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 146 UseRC = ComRC; in EmitCopyFromReg() 162 } else if (UseRC) { in EmitCopyFromReg() 163 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 165 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 103 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 138 if (!UseRC) in EmitCopyFromReg() 139 UseRC = RC; in EmitCopyFromReg() 142 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); in EmitCopyFromReg() 146 UseRC = ComRC; in EmitCopyFromReg() 162 } else if (UseRC) { in EmitCopyFromReg() 163 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 165 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm80/llvm-8.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 104 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 109 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg() 139 if (!UseRC) in EmitCopyFromReg() 140 UseRC = RC; in EmitCopyFromReg() 143 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); in EmitCopyFromReg() 147 UseRC = ComRC; in EmitCopyFromReg() 163 } else if (UseRC) { in EmitCopyFromReg() 164 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 166 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 104 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 109 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg() 139 if (!UseRC) in EmitCopyFromReg() 140 UseRC = RC; in EmitCopyFromReg() 143 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); in EmitCopyFromReg() 147 UseRC = ComRC; in EmitCopyFromReg() 163 } else if (UseRC) { in EmitCopyFromReg() 164 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 166 DstRC = UseRC; in EmitCopyFromReg()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 105 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 110 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 140 if (!UseRC) in EmitCopyFromReg() 141 UseRC = RC; in EmitCopyFromReg() 144 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 148 UseRC = ComRC; in EmitCopyFromReg() 164 } else if (UseRC) { in EmitCopyFromReg() 165 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 167 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 106 const TargetRegisterClass *UseRC = nullptr; in EmitCopyFromReg() local 111 UseRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg() 141 if (!UseRC) in EmitCopyFromReg() 142 UseRC = RC; in EmitCopyFromReg() 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg() 149 UseRC = ComRC; in EmitCopyFromReg() 165 } else if (UseRC) { in EmitCopyFromReg() 166 assert(TRI->isTypeLegalForClass(*UseRC, VT) && in EmitCopyFromReg() 168 DstRC = UseRC; in EmitCopyFromReg()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 468 const TargetRegisterClass *UseRC = in PPCEmitLoad() local 476 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad() 496 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad() 515 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad() 516 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad() 526 ResultReg = createResultReg(UseRC); in PPCEmitLoad() 2424 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local 2428 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, in fastEmitInst_ri() 2438 const TargetRegisterClass *UseRC = in fastEmitInst_r() local 2442 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); in fastEmitInst_r() [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 464 const TargetRegisterClass *UseRC = in PPCEmitLoad() local 472 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad() 492 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad() 511 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad() 512 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad() 522 ResultReg = createResultReg(UseRC); in PPCEmitLoad() 2433 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local 2437 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm); in fastEmitInst_ri() 2446 const TargetRegisterClass *UseRC = in fastEmitInst_r() local 2450 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0); in fastEmitInst_r() [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 469 const TargetRegisterClass *UseRC = in PPCEmitLoad() local 477 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad() 497 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad() 516 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad() 517 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad() 527 ResultReg = createResultReg(UseRC); in PPCEmitLoad() 2423 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local 2427 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, in fastEmitInst_ri() 2437 const TargetRegisterClass *UseRC = in fastEmitInst_r() local 2441 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); in fastEmitInst_r() [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 468 const TargetRegisterClass *UseRC = in PPCEmitLoad() local 476 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad() 496 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad() 515 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad() 516 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad() 526 ResultReg = createResultReg(UseRC); in PPCEmitLoad() 2424 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local 2428 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, in fastEmitInst_ri() 2438 const TargetRegisterClass *UseRC = in fastEmitInst_r() local 2442 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); in fastEmitInst_r() [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 464 const TargetRegisterClass *UseRC = in PPCEmitLoad() local 472 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad() 492 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad() 511 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad() 512 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad() 522 ResultReg = createResultReg(UseRC); in PPCEmitLoad() 2433 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local 2437 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, Op0, Imm); in fastEmitInst_ri() 2446 const TargetRegisterClass *UseRC = in fastEmitInst_r() local 2450 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0); in fastEmitInst_r() [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 467 const TargetRegisterClass *UseRC = in PPCEmitLoad() local 475 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad() 495 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad() 514 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad() 515 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad() 525 ResultReg = createResultReg(UseRC); in PPCEmitLoad() 2436 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local 2440 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, in fastEmitInst_ri() 2450 const TargetRegisterClass *UseRC = in fastEmitInst_r() local 2454 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); in fastEmitInst_r() [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 469 const TargetRegisterClass *UseRC = in PPCEmitLoad() local 477 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); in PPCEmitLoad() 497 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && in PPCEmitLoad() 516 bool IsVSSRC = isVSSRCRegClass(UseRC); in PPCEmitLoad() 517 bool IsVSFRC = isVSFRCRegClass(UseRC); in PPCEmitLoad() 527 ResultReg = createResultReg(UseRC); in PPCEmitLoad() 2423 const TargetRegisterClass *UseRC = in fastEmitInst_ri() local 2427 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC, in fastEmitInst_ri() 2437 const TargetRegisterClass *UseRC = in fastEmitInst_r() local 2441 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill); in fastEmitInst_r() [all …]
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