Home
last modified time | relevance | path

Searched refs:VADDVs (Results 1 – 25 of 33) sorted by relevance

12

/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/ARM/
H A DARMISelLowering.h222 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1722 case ARMISD::VADDVs: return "ARMISD::VADDVs"; in getTargetNodeName()
15031 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
15040 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
15390 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
H A DARMInstrMVE.td690 def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/ARM/
H A DARMISelLowering.h220 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1719 case ARMISD::VADDVs: return "ARMISD::VADDVs"; in getTargetNodeName()
14751 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
15047 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
H A DARMInstrMVE.td615 def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h222 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1729 case ARMISD::VADDVs: return "ARMISD::VADDVs"; in getTargetNodeName()
15075 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
15086 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
15444 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h220 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1719 case ARMISD::VADDVs: return "ARMISD::VADDVs"; in getTargetNodeName()
14754 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
15050 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
H A DARMInstrMVE.td615 def ARMVADDVs : SDNode<"ARMISD::VADDVs", SDTVecReduce>;
/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h222 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1729 case ARMISD::VADDVs: return "ARMISD::VADDVs"; in getTargetNodeName()
15075 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
15086 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
15444 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h232 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1733 MAKE_CASE(ARMISD::VADDVs) in getTargetNodeName()
16128 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
16137 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
16501 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/ARM/
H A DARMISelLowering.h232 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1733 MAKE_CASE(ARMISD::VADDVs) in getTargetNodeName()
16128 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
16137 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
16501 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h232 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1733 MAKE_CASE(ARMISD::VADDVs) in getTargetNodeName()
16128 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
16137 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
16501 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/ARM/
H A DARMISelLowering.h232 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1746 MAKE_CASE(ARMISD::VADDVs) in getTargetNodeName()
13160 case ARMISD::VADDVs: in TryDistrubutionADDVecReduce()
16455 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
16464 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
16790 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h232 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1733 MAKE_CASE(ARMISD::VADDVs) in getTargetNodeName()
16128 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
16137 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
16501 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()
/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/ARM/
H A DARMISelLowering.h232 VADDVs, // sign- or zero-extend the elements of a vector to i32, enumerator
H A DARMISelLowering.cpp1733 MAKE_CASE(ARMISD::VADDVs) in getTargetNodeName()
16128 return DAG.getNode(ARMISD::VADDVs, dl, ResVT, A); in PerformVECREDUCE_ADDCombine()
16137 DAG.getNode(ARMISD::VADDVs, dl, MVT::i32, A)); in PerformVECREDUCE_ADDCombine()
16501 unsigned Opc = Unsigned ? ARMISD::VADDVu : ARMISD::VADDVs; in PerformIntrinsicCombine()

12