1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that ARM uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 16 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/ADT/StringRef.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/ISDOpcodes.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/SelectionDAGNodes.h" 24 #include "llvm/CodeGen/TargetLowering.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/IR/Attributes.h" 27 #include "llvm/IR/CallingConv.h" 28 #include "llvm/IR/Function.h" 29 #include "llvm/IR/IRBuilder.h" 30 #include "llvm/IR/InlineAsm.h" 31 #include "llvm/Support/CodeGen.h" 32 #include "llvm/Support/MachineValueType.h" 33 #include <utility> 34 35 namespace llvm { 36 37 class ARMSubtarget; 38 class DataLayout; 39 class FastISel; 40 class FunctionLoweringInfo; 41 class GlobalValue; 42 class InstrItineraryData; 43 class Instruction; 44 class MachineBasicBlock; 45 class MachineInstr; 46 class SelectionDAG; 47 class TargetLibraryInfo; 48 class TargetMachine; 49 class TargetRegisterInfo; 50 class VectorType; 51 52 namespace ARMISD { 53 54 // ARM Specific DAG Nodes 55 enum NodeType : unsigned { 56 // Start the numbering where the builtin ops and target ops leave off. 57 FIRST_NUMBER = ISD::BUILTIN_OP_END, 58 59 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 60 // TargetExternalSymbol, and TargetGlobalAddress. 61 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 62 // PIC mode. 63 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 64 65 // Add pseudo op to model memcpy for struct byval. 66 COPY_STRUCT_BYVAL, 67 68 CALL, // Function call. 69 CALL_PRED, // Function call that's predicable. 70 CALL_NOLINK, // Function call with branch not branch-and-link. 71 tSECALL, // CMSE non-secure function call. 72 BRCOND, // Conditional branch. 73 BR_JT, // Jumptable branch. 74 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 75 RET_FLAG, // Return with a flag operand. 76 SERET_FLAG, // CMSE Entry function return with a flag operand. 77 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 78 79 PIC_ADD, // Add with a PC operand and a PIC label. 80 81 ASRL, // MVE long arithmetic shift right. 82 LSRL, // MVE long shift right. 83 LSLL, // MVE long shift left. 84 85 CMP, // ARM compare instructions. 86 CMN, // ARM CMN instructions. 87 CMPZ, // ARM compare that sets only Z flag. 88 CMPFP, // ARM VFP compare instruction, sets FPSCR. 89 CMPFPE, // ARM VFP signalling compare instruction, sets FPSCR. 90 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 91 CMPFPEw0, // ARM VFP signalling compare against zero instruction, sets FPSCR. 92 FMSTAT, // ARM fmstat instruction. 93 94 CMOV, // ARM conditional move instructions. 95 SUBS, // Flag-setting subtraction. 96 97 SSAT, // Signed saturation 98 USAT, // Unsigned saturation 99 100 BCC_i64, 101 102 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 103 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 104 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 105 106 ADDC, // Add with carry 107 ADDE, // Add using carry 108 SUBC, // Sub with carry 109 SUBE, // Sub using carry 110 LSLS, // Shift left producing carry 111 112 VMOVRRD, // double to two gprs. 113 VMOVDRR, // Two gprs to double. 114 VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr 115 116 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 117 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 118 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch. 119 120 TC_RETURN, // Tail call return pseudo. 121 122 THREAD_POINTER, 123 124 DYN_ALLOC, // Dynamic allocation on the stack. 125 126 MEMBARRIER_MCR, // Memory barrier (MCR) 127 128 PRELOAD, // Preload 129 130 WIN__CHKSTK, // Windows' __chkstk call to do stack probing. 131 WIN__DBZCHK, // Windows' divide by zero check 132 133 WLS, // Low-overhead loops, While Loop Start 134 LOOP_DEC, // Really a part of LE, performs the sub 135 LE, // Low-overhead loops, Loop End 136 137 PREDICATE_CAST, // Predicate cast for MVE i1 types 138 VECTOR_REG_CAST, // Reinterpret the current contents of a vector register 139 140 VCMP, // Vector compare. 141 VCMPZ, // Vector compare to zero. 142 VTST, // Vector test bits. 143 144 // Vector shift by vector 145 VSHLs, // ...left/right by signed 146 VSHLu, // ...left/right by unsigned 147 148 // Vector shift by immediate: 149 VSHLIMM, // ...left 150 VSHRsIMM, // ...right (signed) 151 VSHRuIMM, // ...right (unsigned) 152 153 // Vector rounding shift by immediate: 154 VRSHRsIMM, // ...right (signed) 155 VRSHRuIMM, // ...right (unsigned) 156 VRSHRNIMM, // ...right narrow 157 158 // Vector saturating shift by immediate: 159 VQSHLsIMM, // ...left (signed) 160 VQSHLuIMM, // ...left (unsigned) 161 VQSHLsuIMM, // ...left (signed to unsigned) 162 VQSHRNsIMM, // ...right narrow (signed) 163 VQSHRNuIMM, // ...right narrow (unsigned) 164 VQSHRNsuIMM, // ...right narrow (signed to unsigned) 165 166 // Vector saturating rounding shift by immediate: 167 VQRSHRNsIMM, // ...right narrow (signed) 168 VQRSHRNuIMM, // ...right narrow (unsigned) 169 VQRSHRNsuIMM, // ...right narrow (signed to unsigned) 170 171 // Vector shift and insert: 172 VSLIIMM, // ...left 173 VSRIIMM, // ...right 174 175 // Vector get lane (VMOV scalar to ARM core register) 176 // (These are used for 8- and 16-bit element types only.) 177 VGETLANEu, // zero-extend vector extract element 178 VGETLANEs, // sign-extend vector extract element 179 180 // Vector move immediate and move negated immediate: 181 VMOVIMM, 182 VMVNIMM, 183 184 // Vector move f32 immediate: 185 VMOVFPIMM, 186 187 // Move H <-> R, clearing top 16 bits 188 VMOVrh, 189 VMOVhr, 190 191 // Vector duplicate: 192 VDUP, 193 VDUPLANE, 194 195 // Vector shuffles: 196 VEXT, // extract 197 VREV64, // reverse elements within 64-bit doublewords 198 VREV32, // reverse elements within 32-bit words 199 VREV16, // reverse elements within 16-bit halfwords 200 VZIP, // zip (interleave) 201 VUZP, // unzip (deinterleave) 202 VTRN, // transpose 203 VTBL1, // 1-register shuffle with mask 204 VTBL2, // 2-register shuffle with mask 205 VMOVN, // MVE vmovn 206 207 // MVE Saturating truncates 208 VQMOVNs, // Vector (V) Saturating (Q) Move and Narrow (N), signed (s) 209 VQMOVNu, // Vector (V) Saturating (Q) Move and Narrow (N), unsigned (u) 210 211 // MVE float <> half converts 212 VCVTN, // MVE vcvt f32 -> f16, truncating into either the bottom or top lanes 213 VCVTL, // MVE vcvt f16 -> f32, extending from either the bottom or top lanes 214 215 // Vector multiply long: 216 VMULLs, // ...signed 217 VMULLu, // ...unsigned 218 219 // MVE reductions 220 VADDVs, // sign- or zero-extend the elements of a vector to i32, 221 VADDVu, // add them all together, and return an i32 of their sum 222 VADDLVs, // sign- or zero-extend elements to i64 and sum, returning 223 VADDLVu, // the low and high 32-bit halves of the sum 224 VADDLVAs, // same as VADDLV[su] but also add an input accumulator 225 VADDLVAu, // provided as low and high halves 226 VADDLVps, // same as VADDLVs but with a v4i1 predicate mask 227 VADDLVpu, // same as VADDLVu but with a v4i1 predicate mask 228 VADDLVAps, // same as VADDLVps but with a v4i1 predicate mask 229 VADDLVApu, // same as VADDLVpu but with a v4i1 predicate mask 230 VMLAVs, 231 VMLAVu, 232 VMLALVs, 233 VMLALVu, 234 VMLALVAs, 235 VMLALVAu, 236 237 SMULWB, // Signed multiply word by half word, bottom 238 SMULWT, // Signed multiply word by half word, top 239 UMLAL, // 64bit Unsigned Accumulate Multiply 240 SMLAL, // 64bit Signed Accumulate Multiply 241 UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply 242 SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16 243 SMLALBT, // 64-bit signed accumulate multiply bottom, top 16 244 SMLALTB, // 64-bit signed accumulate multiply top, bottom 16 245 SMLALTT, // 64-bit signed accumulate multiply top, top 16 246 SMLALD, // Signed multiply accumulate long dual 247 SMLALDX, // Signed multiply accumulate long dual exchange 248 SMLSLD, // Signed multiply subtract long dual 249 SMLSLDX, // Signed multiply subtract long dual exchange 250 SMMLAR, // Signed multiply long, round and add 251 SMMLSR, // Signed multiply long, subtract and round 252 253 // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b stands for. 254 QADD8b, 255 QSUB8b, 256 QADD16b, 257 QSUB16b, 258 259 // Operands of the standard BUILD_VECTOR node are not legalized, which 260 // is fine if BUILD_VECTORs are always lowered to shuffles or other 261 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 262 // operands need to be legalized. Define an ARM-specific version of 263 // BUILD_VECTOR for this purpose. 264 BUILD_VECTOR, 265 266 // Bit-field insert 267 BFI, 268 269 // Vector OR with immediate 270 VORRIMM, 271 // Vector AND with NOT of immediate 272 VBICIMM, 273 274 // Vector bitwise select 275 VBSL, 276 277 // Pseudo-instruction representing a memory copy using ldm/stm 278 // instructions. 279 MEMCPY, 280 281 // V8.1MMainline condition select 282 CSINV, // Conditional select invert. 283 CSNEG, // Conditional select negate. 284 CSINC, // Conditional select increment. 285 286 // Vector load N-element structure to all lanes: 287 VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 288 VLD2DUP, 289 VLD3DUP, 290 VLD4DUP, 291 292 // NEON loads with post-increment base updates: 293 VLD1_UPD, 294 VLD2_UPD, 295 VLD3_UPD, 296 VLD4_UPD, 297 VLD2LN_UPD, 298 VLD3LN_UPD, 299 VLD4LN_UPD, 300 VLD1DUP_UPD, 301 VLD2DUP_UPD, 302 VLD3DUP_UPD, 303 VLD4DUP_UPD, 304 305 // NEON stores with post-increment base updates: 306 VST1_UPD, 307 VST2_UPD, 308 VST3_UPD, 309 VST4_UPD, 310 VST2LN_UPD, 311 VST3LN_UPD, 312 VST4LN_UPD, 313 314 // Load/Store of dual registers 315 LDRD, 316 STRD 317 }; 318 319 } // end namespace ARMISD 320 321 /// Define some predicates that are used for node matching. 322 namespace ARM { 323 324 bool isBitFieldInvertedMask(unsigned v); 325 326 } // end namespace ARM 327 328 //===--------------------------------------------------------------------===// 329 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 330 331 class ARMTargetLowering : public TargetLowering { 332 public: 333 explicit ARMTargetLowering(const TargetMachine &TM, 334 const ARMSubtarget &STI); 335 336 unsigned getJumpTableEncoding() const override; 337 bool useSoftFloat() const override; 338 339 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 340 341 /// ReplaceNodeResults - Replace the results of node with an illegal result 342 /// type with new values built out of custom code. 343 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 344 SelectionDAG &DAG) const override; 345 346 const char *getTargetNodeName(unsigned Opcode) const override; 347 isSelectSupported(SelectSupportKind Kind)348 bool isSelectSupported(SelectSupportKind Kind) const override { 349 // ARM does not support scalar condition selects on vectors. 350 return (Kind != ScalarCondVectorVal); 351 } 352 353 bool isReadOnly(const GlobalValue *GV) const; 354 355 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 356 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 357 EVT VT) const override; 358 359 MachineBasicBlock * 360 EmitInstrWithCustomInserter(MachineInstr &MI, 361 MachineBasicBlock *MBB) const override; 362 363 void AdjustInstrPostInstrSelection(MachineInstr &MI, 364 SDNode *Node) const override; 365 366 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 367 SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; 368 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; 369 SDValue PerformIntrinsicCombine(SDNode *N, DAGCombinerInfo &DCI) const; 370 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 371 372 bool SimplifyDemandedBitsForTargetNode(SDValue Op, 373 const APInt &OriginalDemandedBits, 374 const APInt &OriginalDemandedElts, 375 KnownBits &Known, 376 TargetLoweringOpt &TLO, 377 unsigned Depth) const override; 378 379 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 380 381 /// allowsMisalignedMemoryAccesses - Returns true if the target allows 382 /// unaligned memory accesses of the specified type. Returns whether it 383 /// is "fast" by reference in the second argument. 384 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 385 unsigned Align, 386 MachineMemOperand::Flags Flags, 387 bool *Fast) const override; 388 389 EVT getOptimalMemOpType(const MemOp &Op, 390 const AttributeList &FuncAttributes) const override; 391 392 bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; 393 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; 394 bool isZExtFree(SDValue Val, EVT VT2) const override; 395 bool shouldSinkOperands(Instruction *I, 396 SmallVectorImpl<Use *> &Ops) const override; 397 Type* shouldConvertSplatType(ShuffleVectorInst* SVI) const override; 398 399 bool isFNegFree(EVT VT) const override; 400 401 bool isVectorLoadExtDesirable(SDValue ExtVal) const override; 402 403 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 404 405 406 /// isLegalAddressingMode - Return true if the addressing mode represented 407 /// by AM is legal for this target, for a load/store of the specified type. 408 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 409 Type *Ty, unsigned AS, 410 Instruction *I = nullptr) const override; 411 412 /// getScalingFactorCost - Return the cost of the scaling used in 413 /// addressing mode represented by AM. 414 /// If the AM is supported, the return value must be >= 0. 415 /// If the AM is not supported, the return value must be negative. 416 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 417 unsigned AS) const override; 418 419 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 420 421 /// Returns true if the addressing mode representing by AM is legal 422 /// for the Thumb1 target, for a load/store of the specified type. 423 bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 424 425 /// isLegalICmpImmediate - Return true if the specified immediate is legal 426 /// icmp immediate, that is the target has icmp instructions which can 427 /// compare a register against the immediate without having to materialize 428 /// the immediate into a register. 429 bool isLegalICmpImmediate(int64_t Imm) const override; 430 431 /// isLegalAddImmediate - Return true if the specified immediate is legal 432 /// add immediate, that is the target has add instructions which can 433 /// add a register and the immediate without having to materialize 434 /// the immediate into a register. 435 bool isLegalAddImmediate(int64_t Imm) const override; 436 437 /// getPreIndexedAddressParts - returns true by value, base pointer and 438 /// offset pointer and addressing mode by reference if the node's address 439 /// can be legally represented as pre-indexed load / store address. 440 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 441 ISD::MemIndexedMode &AM, 442 SelectionDAG &DAG) const override; 443 444 /// getPostIndexedAddressParts - returns true by value, base pointer and 445 /// offset pointer and addressing mode by reference if this node can be 446 /// combined with a load / store to form a post-indexed load / store. 447 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 448 SDValue &Offset, ISD::MemIndexedMode &AM, 449 SelectionDAG &DAG) const override; 450 451 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, 452 const APInt &DemandedElts, 453 const SelectionDAG &DAG, 454 unsigned Depth) const override; 455 456 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits, 457 const APInt &DemandedElts, 458 TargetLoweringOpt &TLO) const override; 459 460 bool ExpandInlineAsm(CallInst *CI) const override; 461 462 ConstraintType getConstraintType(StringRef Constraint) const override; 463 464 /// Examine constraint string and operand type and determine a weight value. 465 /// The operand object must already have been set up with the operand type. 466 ConstraintWeight getSingleConstraintMatchWeight( 467 AsmOperandInfo &info, const char *constraint) const override; 468 469 std::pair<unsigned, const TargetRegisterClass *> 470 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 471 StringRef Constraint, MVT VT) const override; 472 473 const char *LowerXConstraint(EVT ConstraintVT) const override; 474 475 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 476 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 477 /// true it means one of the asm constraint of the inline asm instruction 478 /// being processed is 'm'. 479 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 480 std::vector<SDValue> &Ops, 481 SelectionDAG &DAG) const override; 482 483 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)484 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 485 if (ConstraintCode == "Q") 486 return InlineAsm::Constraint_Q; 487 else if (ConstraintCode == "o") 488 return InlineAsm::Constraint_o; 489 else if (ConstraintCode.size() == 2) { 490 if (ConstraintCode[0] == 'U') { 491 switch(ConstraintCode[1]) { 492 default: 493 break; 494 case 'm': 495 return InlineAsm::Constraint_Um; 496 case 'n': 497 return InlineAsm::Constraint_Un; 498 case 'q': 499 return InlineAsm::Constraint_Uq; 500 case 's': 501 return InlineAsm::Constraint_Us; 502 case 't': 503 return InlineAsm::Constraint_Ut; 504 case 'v': 505 return InlineAsm::Constraint_Uv; 506 case 'y': 507 return InlineAsm::Constraint_Uy; 508 } 509 } 510 } 511 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 512 } 513 getSubtarget()514 const ARMSubtarget* getSubtarget() const { 515 return Subtarget; 516 } 517 518 /// getRegClassFor - Return the register class that should be used for the 519 /// specified value type. 520 const TargetRegisterClass * 521 getRegClassFor(MVT VT, bool isDivergent = false) const override; 522 523 /// Returns true if a cast between SrcAS and DestAS is a noop. isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS)524 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 525 // Addrspacecasts are always noops. 526 return true; 527 } 528 529 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize, 530 unsigned &PrefAlign) const override; 531 532 /// createFastISel - This method returns a target specific FastISel object, 533 /// or null if the target does not support "fast" ISel. 534 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 535 const TargetLibraryInfo *libInfo) const override; 536 537 Sched::Preference getSchedulingPreference(SDNode *N) const override; 538 539 bool 540 isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override; 541 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 542 543 /// isFPImmLegal - Returns true if the target can instruction select the 544 /// specified FP immediate natively. If false, the legalizer will 545 /// materialize the FP immediate as a load from a constant pool. 546 bool isFPImmLegal(const APFloat &Imm, EVT VT, 547 bool ForCodeSize = false) const override; 548 549 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 550 const CallInst &I, 551 MachineFunction &MF, 552 unsigned Intrinsic) const override; 553 554 /// Returns true if it is beneficial to convert a load of a constant 555 /// to just the constant itself. 556 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 557 Type *Ty) const override; 558 559 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 560 /// with this index. 561 bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, 562 unsigned Index) const override; 563 shouldFormOverflowOp(unsigned Opcode,EVT VT,bool MathUsed)564 bool shouldFormOverflowOp(unsigned Opcode, EVT VT, 565 bool MathUsed) const override { 566 // Using overflow ops for overflow checks only should beneficial on ARM. 567 return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); 568 } 569 570 /// Returns true if an argument of type Ty needs to be passed in a 571 /// contiguous block of registers in calling convention CallConv. 572 bool functionArgumentNeedsConsecutiveRegisters( 573 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override; 574 575 /// If a physical register, this returns the register that receives the 576 /// exception address on entry to an EH pad. 577 Register 578 getExceptionPointerRegister(const Constant *PersonalityFn) const override; 579 580 /// If a physical register, this returns the register that receives the 581 /// exception typeid on entry to a landing pad. 582 Register 583 getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 584 585 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; 586 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, 587 AtomicOrdering Ord) const override; 588 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, 589 Value *Addr, AtomicOrdering Ord) const override; 590 591 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; 592 593 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, 594 AtomicOrdering Ord) const override; 595 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, 596 AtomicOrdering Ord) const override; 597 598 unsigned getMaxSupportedInterleaveFactor() const override; 599 600 bool lowerInterleavedLoad(LoadInst *LI, 601 ArrayRef<ShuffleVectorInst *> Shuffles, 602 ArrayRef<unsigned> Indices, 603 unsigned Factor) const override; 604 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, 605 unsigned Factor) const override; 606 607 bool shouldInsertFencesForAtomic(const Instruction *I) const override; 608 TargetLoweringBase::AtomicExpansionKind 609 shouldExpandAtomicLoadInIR(LoadInst *LI) const override; 610 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 611 TargetLoweringBase::AtomicExpansionKind 612 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 613 TargetLoweringBase::AtomicExpansionKind 614 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; 615 616 bool useLoadStackGuardNode() const override; 617 618 void insertSSPDeclarations(Module &M) const override; 619 Value *getSDagStackGuard(const Module &M) const override; 620 Function *getSSPStackGuardCheck(const Module &M) const override; 621 622 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx, 623 unsigned &Cost) const override; 624 canMergeStoresTo(unsigned AddressSpace,EVT MemVT,const SelectionDAG & DAG)625 bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, 626 const SelectionDAG &DAG) const override { 627 // Do not merge to larger than i32. 628 return (MemVT.getSizeInBits() <= 32); 629 } 630 631 bool isCheapToSpeculateCttz() const override; 632 bool isCheapToSpeculateCtlz() const override; 633 convertSetCCLogicToBitwiseLogic(EVT VT)634 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override { 635 return VT.isScalarInteger(); 636 } 637 supportSwiftError()638 bool supportSwiftError() const override { 639 return true; 640 } 641 hasStandaloneRem(EVT VT)642 bool hasStandaloneRem(EVT VT) const override { 643 return HasStandaloneRem; 644 } 645 646 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override; 647 648 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const; 649 CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const; 650 651 /// Returns true if \p VecTy is a legal interleaved access type. This 652 /// function checks the vector element type and the overall width of the 653 /// vector. 654 bool isLegalInterleavedAccessType(unsigned Factor, FixedVectorType *VecTy, 655 const DataLayout &DL) const; 656 657 bool alignLoopsWithOptSize() const override; 658 659 /// Returns the number of interleaved accesses that will be generated when 660 /// lowering accesses of the given type. 661 unsigned getNumInterleavedAccesses(VectorType *VecTy, 662 const DataLayout &DL) const; 663 664 void finalizeLowering(MachineFunction &MF) const override; 665 666 /// Return the correct alignment for the current calling convention. 667 Align getABIAlignmentForCallingConv(Type *ArgTy, 668 DataLayout DL) const override; 669 670 bool isDesirableToCommuteWithShift(const SDNode *N, 671 CombineLevel Level) const override; 672 673 bool shouldFoldConstantShiftPairToMask(const SDNode *N, 674 CombineLevel Level) const override; 675 676 bool preferIncOfAddToSubOfNot(EVT VT) const override; 677 678 protected: 679 std::pair<const TargetRegisterClass *, uint8_t> 680 findRepresentativeClass(const TargetRegisterInfo *TRI, 681 MVT VT) const override; 682 683 private: 684 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 685 /// make the right decision when generating code for different targets. 686 const ARMSubtarget *Subtarget; 687 688 const TargetRegisterInfo *RegInfo; 689 690 const InstrItineraryData *Itins; 691 692 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 693 unsigned ARMPCLabelIndex; 694 695 // TODO: remove this, and have shouldInsertFencesForAtomic do the proper 696 // check. 697 bool InsertFencesForAtomic; 698 699 bool HasStandaloneRem = true; 700 701 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 702 void addDRTypeForNEON(MVT VT); 703 void addQRTypeForNEON(MVT VT); 704 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const; 705 706 using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>; 707 708 void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain, 709 SDValue &Arg, RegsToPassVector &RegsToPass, 710 CCValAssign &VA, CCValAssign &NextVA, 711 SDValue &StackPtr, 712 SmallVectorImpl<SDValue> &MemOpChains, 713 ISD::ArgFlagsTy Flags) const; 714 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 715 SDValue &Root, SelectionDAG &DAG, 716 const SDLoc &dl) const; 717 718 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC, 719 bool isVarArg) const; 720 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 721 bool isVarArg) const; 722 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 723 const SDLoc &dl, SelectionDAG &DAG, 724 const CCValAssign &VA, 725 ISD::ArgFlagsTy Flags) const; 726 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 727 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 728 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const; 729 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG, 730 const ARMSubtarget *Subtarget) const; 731 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 732 const ARMSubtarget *Subtarget) const; 733 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 734 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 735 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 736 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 737 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 738 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const; 739 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 740 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 741 SelectionDAG &DAG) const; 742 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 743 SelectionDAG &DAG, 744 TLSModel::Model model) const; 745 SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 746 SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const; 747 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 748 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 749 SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const; 750 SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const; 751 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 752 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 753 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 754 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 755 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 756 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 757 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 758 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 759 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 760 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 761 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 762 const ARMSubtarget *ST) const; 763 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 764 const ARMSubtarget *ST) const; 765 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 766 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 767 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 768 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const; 769 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed, 770 SmallVectorImpl<SDValue> &Results) const; 771 SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG, 772 const ARMSubtarget *Subtarget) const; 773 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed, 774 SDValue &Chain) const; 775 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const; 776 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 777 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const; 778 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const; 779 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const; 780 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 781 SDValue LowerFSETCC(SDValue Op, SelectionDAG &DAG) const; 782 void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results, 783 SelectionDAG &DAG) const; 784 void LowerLOAD(SDNode *N, SmallVectorImpl<SDValue> &Results, 785 SelectionDAG &DAG) const; 786 787 Register getRegisterByName(const char* RegName, LLT VT, 788 const MachineFunction &MF) const override; 789 790 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, 791 SmallVectorImpl<SDNode *> &Created) const override; 792 793 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 794 EVT VT) const override; 795 796 SDValue MoveToHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, MVT ValVT, 797 SDValue Val) const; 798 SDValue MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG, MVT LocVT, 799 MVT ValVT, SDValue Val) const; 800 801 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 802 803 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 804 CallingConv::ID CallConv, bool isVarArg, 805 const SmallVectorImpl<ISD::InputArg> &Ins, 806 const SDLoc &dl, SelectionDAG &DAG, 807 SmallVectorImpl<SDValue> &InVals, bool isThisReturn, 808 SDValue ThisVal) const; 809 supportSplitCSR(MachineFunction * MF)810 bool supportSplitCSR(MachineFunction *MF) const override { 811 return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS && 812 MF->getFunction().hasFnAttribute(Attribute::NoUnwind); 813 } 814 815 void initializeSplitCSR(MachineBasicBlock *Entry) const override; 816 void insertCopiesSplitCSR( 817 MachineBasicBlock *Entry, 818 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 819 820 bool 821 splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, 822 SDValue *Parts, unsigned NumParts, MVT PartVT, 823 Optional<CallingConv::ID> CC) const override; 824 825 SDValue 826 joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, 827 const SDValue *Parts, unsigned NumParts, 828 MVT PartVT, EVT ValueVT, 829 Optional<CallingConv::ID> CC) const override; 830 831 SDValue 832 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 833 const SmallVectorImpl<ISD::InputArg> &Ins, 834 const SDLoc &dl, SelectionDAG &DAG, 835 SmallVectorImpl<SDValue> &InVals) const override; 836 837 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl, 838 SDValue &Chain, const Value *OrigArg, 839 unsigned InRegsParamRecordIdx, int ArgOffset, 840 unsigned ArgSize) const; 841 842 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 843 const SDLoc &dl, SDValue &Chain, 844 unsigned ArgOffset, unsigned TotalArgRegsSaveSize, 845 bool ForceMutable = false) const; 846 847 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 848 SmallVectorImpl<SDValue> &InVals) const override; 849 850 /// HandleByVal - Target-specific cleanup for ByVal support. 851 void HandleByVal(CCState *, unsigned &, Align) const override; 852 853 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 854 /// for tail call optimization. Targets which want to do tail call 855 /// optimization should implement this function. 856 bool IsEligibleForTailCallOptimization( 857 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, 858 bool isCalleeStructRet, bool isCallerStructRet, 859 const SmallVectorImpl<ISD::OutputArg> &Outs, 860 const SmallVectorImpl<SDValue> &OutVals, 861 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG, 862 const bool isIndirect) const; 863 864 bool CanLowerReturn(CallingConv::ID CallConv, 865 MachineFunction &MF, bool isVarArg, 866 const SmallVectorImpl<ISD::OutputArg> &Outs, 867 LLVMContext &Context) const override; 868 869 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 870 const SmallVectorImpl<ISD::OutputArg> &Outs, 871 const SmallVectorImpl<SDValue> &OutVals, 872 const SDLoc &dl, SelectionDAG &DAG) const override; 873 874 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 875 876 bool mayBeEmittedAsTailCall(const CallInst *CI) const override; 877 shouldConsiderGEPOffsetSplit()878 bool shouldConsiderGEPOffsetSplit() const override { return true; } 879 880 bool isUnsupportedFloatingType(EVT VT) const; 881 882 SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal, 883 SDValue ARMcc, SDValue CCR, SDValue Cmp, 884 SelectionDAG &DAG) const; 885 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 886 SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const; 887 SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 888 const SDLoc &dl, bool Signaling = false) const; 889 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 890 891 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 892 893 void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB, 894 MachineBasicBlock *DispatchBB, int FI) const; 895 896 void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const; 897 898 bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const; 899 900 MachineBasicBlock *EmitStructByval(MachineInstr &MI, 901 MachineBasicBlock *MBB) const; 902 903 MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI, 904 MachineBasicBlock *MBB) const; 905 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI, 906 MachineBasicBlock *MBB) const; 907 void addMVEVectorTypes(bool HasMVEFP); 908 void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action); 909 void setAllExpand(MVT VT); 910 }; 911 912 enum VMOVModImmType { 913 VMOVModImm, 914 VMVNModImm, 915 MVEVMVNModImm, 916 OtherModImm 917 }; 918 919 namespace ARM { 920 921 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 922 const TargetLibraryInfo *libInfo); 923 924 } // end namespace ARM 925 926 } // end namespace llvm 927 928 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H 929